Digital Calibration Algorithm of Conversion Error Influenced by Parasitic Capacitance in C-C SAR-ADC Based on γ-Estimation

C-C successive approximation register analog-to-digital converter (C-C SAR-ADC) is space-saving architecture compared to SAR-ADC with binary weighted capacitive digital-to-analog converter (CDAC). However, the accuracy of C-C SAR-ADC is degraded due to parasitic capacitance of floating nodes. This p...

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Veröffentlicht in:	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Communications and Computer Sciences, 2021/02/01, Vol.E104.A(2), pp.516-524
Hauptverfasser:	SEKINE, Satoshi, MATSUURA, Tatsuji, KISHIDA, Ryo, HYOGO, Akira
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithms Analog to digital conversion Analog to digital converters analog-to-digital converter (ADC) C-C SAR-ADC Capacitance digital correction Digital to analog conversion Digital to analog converters digital-to-analog converter (DAC) Linearity Parasitics (electronics) successive approximation register ADC (SAR-ADC) γ-estimation
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