Optical Versus Electrical: Performance Evaluation of Network On-Chip Topologies for UWASN Manycore Processors

Optical network on chip (ONoC) has evolved as an innovative technology for on-chip interconnects that can fulfill the upcoming requirements of manycore processors used in UWASN. The objective of this paper is two-fold, first we assessed the performance of electrical and optical NoC mesh and torus topologies with 64 and 144 nodes. We explored the impact of different packet and network sizes on average latency and throughput of NoCs. Furthermore, we investigated the effect of application mapping on crosstalk noise, laser power consumption and SNR for optical mesh/torus architectures under real time benchmark applications. The experimental outcomes revealed that ONoC has advantages of improved average latency and improved throughput for large packet size. Second, we proposed a hybrid optical–electrical NoC topology based on multi write single read serpentine optical bus architecture aiming to minimize the communication latency and energy consumption. We present an optimized routing algorithm for the proposed topology that exploits the advantage of processing parallelism level to reduce latency in hybrid network. The proposed topology proved to be 48% and 53% efficient in latency, 12% and 17% higher in throughput and provides 54% and 23% reduction in energy consumption under uniform random and hotspot traffic patterns respectively as compared to other NoC architectures.