A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration

In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional- {N} multiplying delay-locked loop(MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed, and a two-stage synthesizable DTC is proposed in which a path-selection DTC is used as the coarse stage and a va...

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Veröffentlicht in:	IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2021-02, Vol.68 (2), p.603-616
Hauptverfasser:	Liu, Bangan, Zhang, Yuncheng, Qiu, Junjun, Ngo, Huy Cu, Deng, Wei, Nakata, Kengo, Yoshioka, Toru, Emmei, Jun, Pang, Jian, Narayanan, Aravind Tharayil, Zhang, Haosheng, Someya, Teruki, Shirane, Atsushi, Okada, Kenichi
Format:	Artikel
Sprache:	eng
Schlagworte:	Analog circuits bang-bang phase detector (BBPD) Calibration Circuit design Co-design Computer architecture Delays digital-to-time converter (DTC) fully-synthesizable injection locking Interpolation Jitter Linearity Multiplying delay-locked loop (MDLL) Nonlinearity nonlinearity calibration Offsets path-selection DTC Phase detectors Phase locked loops phase offset phase-locked loop (PLL) Power consumption Power demand Reactive power Synthesis variable-slope DTC Vibration
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