A Fast Locking 5.8-7.2-GHz Fractional-N Synthesizer With Sub-2-us Settling in 22-nm FDSOI
This letter presents a fast frequency hopping all-digital fractional-N synthesizer with linear frequency tuning word estimation and aggressive type-I and type-II loop settling. It has a linearized DCO allowing wide-band and closed-loop operation and employs digital zero-phase reset to reduce phase t...
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| Veröffentlicht in: | IEEE solid-state circuits letters 2020, Vol.3, p.546-549 |
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| creator | Prinzie, Jeffrey Andrabi, Shuja Beghein, Christophe Cao, Changhua Chen, Hsinhua Guo, Xiaochuan Strange, Jon Tenbroek, Bernard |
| description | This letter presents a fast frequency hopping all-digital fractional-N synthesizer with linear frequency tuning word estimation and aggressive type-I and type-II loop settling. It has a linearized DCO allowing wide-band and closed-loop operation and employs digital zero-phase reset to reduce phase transients during switch over due to type-I settling. The DCO gain is equalized by exploiting routing inductances and a hybrid binary-thermometric segmentation provides improved DNL performance for closed-loop operation in a 5.8-7.2-GHz range. The circuit was processed in a 22-nm FDSOI technology and achieves a settling time below 2~\mu \text{s} in a 200-MHz hopping range. |
| doi_str_mv | 10.1109/LSSC.2020.3036122 |
| format | Article |
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It has a linearized DCO allowing wide-band and closed-loop operation and employs digital zero-phase reset to reduce phase transients during switch over due to type-I settling. The DCO gain is equalized by exploiting routing inductances and a hybrid binary-thermometric segmentation provides improved DNL performance for closed-loop operation in a 5.8-7.2-GHz range. The circuit was processed in a 22-nm FDSOI technology and achieves a settling time below <inline-formula> <tex-math notation="LaTeX">2~\mu \text{s} </tex-math></inline-formula> in a 200-MHz hopping range.</description><identifier>ISSN: 2573-9603</identifier><identifier>EISSN: 2573-9603</identifier><identifier>DOI: 10.1109/LSSC.2020.3036122</identifier><identifier>CODEN: ISCLCN</identifier><language>eng</language><publisher>Piscataway: IEEE</publisher><subject>All-digital PLL (ADPLL) ; Circuits ; digitally controlled oscillator ; fractional-N synthesizer ; Frequency estimation ; Frequency hopping ; Frequency synthesizers ; lock time ; Locking ; Phase noise ; Segmentation ; Settling ; Silicon-on-insulator ; Synthesis ; Synthesizers ; Transient analysis ; Tuning</subject><ispartof>IEEE solid-state circuits letters, 2020, Vol.3, p.546-549</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2020</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c336t-ef91de77ea9e174f8f8417e54dacb3402d16f4f8dc06c5745a1f1c0557e530483</citedby><cites>FETCH-LOGICAL-c336t-ef91de77ea9e174f8f8417e54dacb3402d16f4f8dc06c5745a1f1c0557e530483</cites><orcidid>0000-0002-6920-6280 ; 0000-0002-5975-9682 ; 0000-0003-1147-8432 ; 0000-0002-7303-985X</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9249420$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,4024,27923,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9249420$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Prinzie, Jeffrey</creatorcontrib><creatorcontrib>Andrabi, Shuja</creatorcontrib><creatorcontrib>Beghein, Christophe</creatorcontrib><creatorcontrib>Cao, Changhua</creatorcontrib><creatorcontrib>Chen, Hsinhua</creatorcontrib><creatorcontrib>Guo, Xiaochuan</creatorcontrib><creatorcontrib>Strange, Jon</creatorcontrib><creatorcontrib>Tenbroek, Bernard</creatorcontrib><title>A Fast Locking 5.8-7.2-GHz Fractional-N Synthesizer With Sub-2-us Settling in 22-nm FDSOI</title><title>IEEE solid-state circuits letters</title><addtitle>LSSC</addtitle><description>This letter presents a fast frequency hopping all-digital fractional-N synthesizer with linear frequency tuning word estimation and aggressive type-I and type-II loop settling. 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The circuit was processed in a 22-nm FDSOI technology and achieves a settling time below <inline-formula> <tex-math notation="LaTeX">2~\mu \text{s} </tex-math></inline-formula> in a 200-MHz hopping range.</description><subject>All-digital PLL (ADPLL)</subject><subject>Circuits</subject><subject>digitally controlled oscillator</subject><subject>fractional-N synthesizer</subject><subject>Frequency estimation</subject><subject>Frequency hopping</subject><subject>Frequency synthesizers</subject><subject>lock time</subject><subject>Locking</subject><subject>Phase noise</subject><subject>Segmentation</subject><subject>Settling</subject><subject>Silicon-on-insulator</subject><subject>Synthesis</subject><subject>Synthesizers</subject><subject>Transient analysis</subject><subject>Tuning</subject><issn>2573-9603</issn><issn>2573-9603</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpNkE1Lw0AQhhdRsNT-APGy4Hnj7Ec22WOppi0Ee4ginpZ0s7GpbVJ3k0P7601oEU_zMjzvMDwI3VMIKAX1lGbZLGDAIODAJWXsCo1YGHGiJPDrf_kWTbzfAgBVVHKIR-hzipPctzhtzHdVf-EwiEkUMDJfnHDictNWTZ3vyCvOjnW7sb46WYc_qnaDs25NGOk8zmzb7oZuVWPGSL3HyXO2Wt6hmzLfeTu5zDF6T17eZguSrubL2TQlhnPZElsqWtgosrmyNBJlXMaCRjYURW7WXAArqCz7dWFAmjASYU5LaiAMe4aDiPkYPZ7vHlzz01nf6m3Tuf5pr5mQSkSSgewpeqaMa7x3ttQHV-1zd9QU9CBRDxL1IFFfJPadh3Onstb-8YoJJRjwXxuHaR0</recordid><startdate>2020</startdate><enddate>2020</enddate><creator>Prinzie, Jeffrey</creator><creator>Andrabi, Shuja</creator><creator>Beghein, Christophe</creator><creator>Cao, Changhua</creator><creator>Chen, Hsinhua</creator><creator>Guo, Xiaochuan</creator><creator>Strange, Jon</creator><creator>Tenbroek, Bernard</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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| subjects | All-digital PLL (ADPLL) Circuits digitally controlled oscillator fractional-N synthesizer Frequency estimation Frequency hopping Frequency synthesizers lock time Locking Phase noise Segmentation Settling Silicon-on-insulator Synthesis Synthesizers Transient analysis Tuning |
| title | A Fast Locking 5.8-7.2-GHz Fractional-N Synthesizer With Sub-2-us Settling in 22-nm FDSOI |
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