Controlling the relaxation mechanism of low strain Si1−xGex/Si(001) layers and reducing the threading dislocation density by providing a preexisting dislocation source
Strain relaxed Si 1 − x Ge x buffer layers on Si(001) can be used as virtual substrates for the growth of both strained Si and strained SiGe, which are suitable materials for sub-7 nm CMOS devices due to their enhanced carrier mobility. For industrial applications, the threading dislocation density...
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creator | Becker, L. Storck, P. Schulz, T. Zoellner, M. H. Di Gaspare, L. Rovaris, F. Marzegalli, A. Montalenti, F. De Seta, M. Capellini, G. Schwalb, G. Schroeder, T. Albrecht, M. |
description | Strain relaxed
Si
1
−
x
Ge
x buffer layers on Si(001) can be used as virtual substrates for the growth of both strained Si and strained SiGe, which are suitable materials for sub-7 nm CMOS devices due to their enhanced carrier mobility. For industrial applications, the threading dislocation density (TDD) has to be as low as possible. However, a reduction of the TDD is limited by the balance between dislocation glide and nucleation as well as dislocation blocking. The relaxation mechanism of low strain
Si
0.98
Ge
0.02 layers on commercial substrates is compared to substrates with a predeposited SiGe backside layer, which provides threading dislocations at the edge of the wafer. It is shown that by the exploitation of this reservoir, the critical thickness for plastic relaxation is reduced and the formation of misfit dislocation bundles can be prevented. Instead, upon reaching the critical thickness, these preexisting dislocations simultaneously glide unhindered from the edge of the wafer toward the center. The resulting dislocation network is free of thick dislocation bundles that cause pileups, and the TDD can be reduced by one order of magnitude. |
doi_str_mv | 10.1063/5.0032454 |
format | Article |
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Si
1
−
x
Ge
x buffer layers on Si(001) can be used as virtual substrates for the growth of both strained Si and strained SiGe, which are suitable materials for sub-7 nm CMOS devices due to their enhanced carrier mobility. For industrial applications, the threading dislocation density (TDD) has to be as low as possible. However, a reduction of the TDD is limited by the balance between dislocation glide and nucleation as well as dislocation blocking. The relaxation mechanism of low strain
Si
0.98
Ge
0.02 layers on commercial substrates is compared to substrates with a predeposited SiGe backside layer, which provides threading dislocations at the edge of the wafer. It is shown that by the exploitation of this reservoir, the critical thickness for plastic relaxation is reduced and the formation of misfit dislocation bundles can be prevented. Instead, upon reaching the critical thickness, these preexisting dislocations simultaneously glide unhindered from the edge of the wafer toward the center. The resulting dislocation network is free of thick dislocation bundles that cause pileups, and the TDD can be reduced by one order of magnitude.</description><identifier>ISSN: 0021-8979</identifier><identifier>EISSN: 1089-7550</identifier><identifier>DOI: 10.1063/5.0032454</identifier><identifier>CODEN: JAPIAU</identifier><language>eng</language><publisher>MELVILLE: Amer Inst Physics</publisher><subject>Applied physics ; Buffer layers ; Bundles ; Carrier mobility ; CMOS ; Dislocation density ; Industrial applications ; Misfit dislocations ; Nucleation ; Physical Sciences ; Physics ; Physics, Applied ; Science & Technology ; Silicon germanides ; Substrates ; Thickness ; Threading dislocations</subject><ispartof>Journal of applied physics, 2020-12, Vol.128 (21), Article 215305</ispartof><rights>Author(s)</rights><rights>2020 Author(s). Published under license by AIP Publishing.</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>true</woscitedreferencessubscribed><woscitedreferencescount>7</woscitedreferencescount><woscitedreferencesoriginalsourcerecordid>wos000597312500003</woscitedreferencesoriginalsourcerecordid><cites>FETCH-LOGICAL-p218t-19907f5e23900ce71b6d7bf090e24a24a5e904659aa861efa06ad3cafdf32a7b3</cites><orcidid>0000-0002-5169-2823 ; 0000-0002-9514-233X ; 0000-0002-4208-2599 ; 0000-0002-0729-5409 ; 0000-0003-1835-052X ; 0000-0003-1509-3476 ; 0000-0001-7854-8269 ; 0000-0002-8920-8371 ; 0000-0003-3134-7296</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://pubs.aip.org/jap/article-lookup/doi/10.1063/5.0032454$$EHTML$$P50$$Gscitation$$H</linktohtml><link.rule.ids>314,780,784,794,4512,27924,27925,76384</link.rule.ids></links><search><creatorcontrib>Becker, L.</creatorcontrib><creatorcontrib>Storck, P.</creatorcontrib><creatorcontrib>Schulz, T.</creatorcontrib><creatorcontrib>Zoellner, M. H.</creatorcontrib><creatorcontrib>Di Gaspare, L.</creatorcontrib><creatorcontrib>Rovaris, F.</creatorcontrib><creatorcontrib>Marzegalli, A.</creatorcontrib><creatorcontrib>Montalenti, F.</creatorcontrib><creatorcontrib>De Seta, M.</creatorcontrib><creatorcontrib>Capellini, G.</creatorcontrib><creatorcontrib>Schwalb, G.</creatorcontrib><creatorcontrib>Schroeder, T.</creatorcontrib><creatorcontrib>Albrecht, M.</creatorcontrib><title>Controlling the relaxation mechanism of low strain Si1−xGex/Si(001) layers and reducing the threading dislocation density by providing a preexisting dislocation source</title><title>Journal of applied physics</title><addtitle>J APPL PHYS</addtitle><description>Strain relaxed
Si
1
−
x
Ge
x buffer layers on Si(001) can be used as virtual substrates for the growth of both strained Si and strained SiGe, which are suitable materials for sub-7 nm CMOS devices due to their enhanced carrier mobility. For industrial applications, the threading dislocation density (TDD) has to be as low as possible. However, a reduction of the TDD is limited by the balance between dislocation glide and nucleation as well as dislocation blocking. The relaxation mechanism of low strain
Si
0.98
Ge
0.02 layers on commercial substrates is compared to substrates with a predeposited SiGe backside layer, which provides threading dislocations at the edge of the wafer. It is shown that by the exploitation of this reservoir, the critical thickness for plastic relaxation is reduced and the formation of misfit dislocation bundles can be prevented. Instead, upon reaching the critical thickness, these preexisting dislocations simultaneously glide unhindered from the edge of the wafer toward the center. The resulting dislocation network is free of thick dislocation bundles that cause pileups, and the TDD can be reduced by one order of magnitude.</description><subject>Applied physics</subject><subject>Buffer layers</subject><subject>Bundles</subject><subject>Carrier mobility</subject><subject>CMOS</subject><subject>Dislocation density</subject><subject>Industrial applications</subject><subject>Misfit dislocations</subject><subject>Nucleation</subject><subject>Physical Sciences</subject><subject>Physics</subject><subject>Physics, Applied</subject><subject>Science & Technology</subject><subject>Silicon germanides</subject><subject>Substrates</subject><subject>Thickness</subject><subject>Threading dislocations</subject><issn>0021-8979</issn><issn>1089-7550</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><sourceid>AOWDO</sourceid><recordid>eNqNkc9u1DAQxi0EEsvCgTewxIU_Sju24yQ-oggKUiUOhXM0SSasq6y92N529w048xa8Fk-C2xSQOCAkSzMe_b5vPB7Gngo4EVCpU30CoGSpy3tsJaAxRa013GcrACmKxtTmIXsU4yWAEI0yK_a99S4FP8_WfeZpQzzQjAdM1ju-pWGDzsYt9xOf_TWPKaB1_MKKH1-_Hc7ocHphn2erF3zGI4XI0Y3ZYNwPv9zSJhCON7fRxtkPi_FILtp05P2R74K_srcA5pzoYGP6G49-HwZ6zB5MOEd6chfX7NPbNx_bd8X5h7P37evzYidFkwphDNSTJqkMwEC16Kux7icwQLLEfDQZKCttEJtK0IRQ4agGnMZJSax7tWbPFt_8tC97iqm7zP1dbtnJsqqlqkT-4jV7tVDX1PspDpbcQN0u2C2GYwcA2tRKSJ0zUJlu_p9ubbqdu_V7l7L05SLNqqX-Wyegu9l5p7u7nf8LvvLhD9jt8rQ_AfW3ru4</recordid><startdate>20201207</startdate><enddate>20201207</enddate><creator>Becker, L.</creator><creator>Storck, P.</creator><creator>Schulz, T.</creator><creator>Zoellner, M. H.</creator><creator>Di Gaspare, L.</creator><creator>Rovaris, F.</creator><creator>Marzegalli, A.</creator><creator>Montalenti, F.</creator><creator>De Seta, M.</creator><creator>Capellini, G.</creator><creator>Schwalb, G.</creator><creator>Schroeder, T.</creator><creator>Albrecht, M.</creator><general>Amer Inst Physics</general><general>American Institute of Physics</general><scope>AOWDO</scope><scope>BLEPL</scope><scope>DTL</scope><scope>8FD</scope><scope>H8D</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-5169-2823</orcidid><orcidid>https://orcid.org/0000-0002-9514-233X</orcidid><orcidid>https://orcid.org/0000-0002-4208-2599</orcidid><orcidid>https://orcid.org/0000-0002-0729-5409</orcidid><orcidid>https://orcid.org/0000-0003-1835-052X</orcidid><orcidid>https://orcid.org/0000-0003-1509-3476</orcidid><orcidid>https://orcid.org/0000-0001-7854-8269</orcidid><orcidid>https://orcid.org/0000-0002-8920-8371</orcidid><orcidid>https://orcid.org/0000-0003-3134-7296</orcidid></search><sort><creationdate>20201207</creationdate><title>Controlling the relaxation mechanism of low strain Si1−xGex/Si(001) layers and reducing the threading dislocation density by providing a preexisting dislocation source</title><author>Becker, L. ; Storck, P. ; Schulz, T. ; Zoellner, M. H. ; Di Gaspare, L. ; Rovaris, F. ; Marzegalli, A. ; Montalenti, F. ; De Seta, M. ; Capellini, G. ; Schwalb, G. ; Schroeder, T. ; Albrecht, M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-p218t-19907f5e23900ce71b6d7bf090e24a24a5e904659aa861efa06ad3cafdf32a7b3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2020</creationdate><topic>Applied physics</topic><topic>Buffer layers</topic><topic>Bundles</topic><topic>Carrier mobility</topic><topic>CMOS</topic><topic>Dislocation density</topic><topic>Industrial applications</topic><topic>Misfit dislocations</topic><topic>Nucleation</topic><topic>Physical Sciences</topic><topic>Physics</topic><topic>Physics, Applied</topic><topic>Science & Technology</topic><topic>Silicon germanides</topic><topic>Substrates</topic><topic>Thickness</topic><topic>Threading dislocations</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Becker, L.</creatorcontrib><creatorcontrib>Storck, P.</creatorcontrib><creatorcontrib>Schulz, T.</creatorcontrib><creatorcontrib>Zoellner, M. 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H.</au><au>Di Gaspare, L.</au><au>Rovaris, F.</au><au>Marzegalli, A.</au><au>Montalenti, F.</au><au>De Seta, M.</au><au>Capellini, G.</au><au>Schwalb, G.</au><au>Schroeder, T.</au><au>Albrecht, M.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Controlling the relaxation mechanism of low strain Si1−xGex/Si(001) layers and reducing the threading dislocation density by providing a preexisting dislocation source</atitle><jtitle>Journal of applied physics</jtitle><stitle>J APPL PHYS</stitle><date>2020-12-07</date><risdate>2020</risdate><volume>128</volume><issue>21</issue><artnum>215305</artnum><issn>0021-8979</issn><eissn>1089-7550</eissn><coden>JAPIAU</coden><abstract>Strain relaxed
Si
1
−
x
Ge
x buffer layers on Si(001) can be used as virtual substrates for the growth of both strained Si and strained SiGe, which are suitable materials for sub-7 nm CMOS devices due to their enhanced carrier mobility. For industrial applications, the threading dislocation density (TDD) has to be as low as possible. However, a reduction of the TDD is limited by the balance between dislocation glide and nucleation as well as dislocation blocking. The relaxation mechanism of low strain
Si
0.98
Ge
0.02 layers on commercial substrates is compared to substrates with a predeposited SiGe backside layer, which provides threading dislocations at the edge of the wafer. It is shown that by the exploitation of this reservoir, the critical thickness for plastic relaxation is reduced and the formation of misfit dislocation bundles can be prevented. Instead, upon reaching the critical thickness, these preexisting dislocations simultaneously glide unhindered from the edge of the wafer toward the center. The resulting dislocation network is free of thick dislocation bundles that cause pileups, and the TDD can be reduced by one order of magnitude.</abstract><cop>MELVILLE</cop><pub>Amer Inst Physics</pub><doi>10.1063/5.0032454</doi><tpages>9</tpages><orcidid>https://orcid.org/0000-0002-5169-2823</orcidid><orcidid>https://orcid.org/0000-0002-9514-233X</orcidid><orcidid>https://orcid.org/0000-0002-4208-2599</orcidid><orcidid>https://orcid.org/0000-0002-0729-5409</orcidid><orcidid>https://orcid.org/0000-0003-1835-052X</orcidid><orcidid>https://orcid.org/0000-0003-1509-3476</orcidid><orcidid>https://orcid.org/0000-0001-7854-8269</orcidid><orcidid>https://orcid.org/0000-0002-8920-8371</orcidid><orcidid>https://orcid.org/0000-0003-3134-7296</orcidid><oa>free_for_read</oa></addata></record> |
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source | AIP Journals Complete; Alma/SFX Local Collection |
subjects | Applied physics Buffer layers Bundles Carrier mobility CMOS Dislocation density Industrial applications Misfit dislocations Nucleation Physical Sciences Physics Physics, Applied Science & Technology Silicon germanides Substrates Thickness Threading dislocations |
title | Controlling the relaxation mechanism of low strain Si1−xGex/Si(001) layers and reducing the threading dislocation density by providing a preexisting dislocation source |
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