A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC With Double Clock-Rate Coarse Decision
A SAR-assisted SAR ADC that uses a double clock-rate coarse decision technique is presented. The coarse ADC operates with a higher rate clock to reduce the MSBs decision time. The mismatch problem between coarse and fine ADCs is solved by using redundancy and background offset calibration. A simple...
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| Veröffentlicht in: | IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2020-12, Vol.67 (12), p.2833-2837 |
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| container_issue | 12 |
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| container_title | IEEE transactions on circuits and systems. II, Express briefs |
| container_volume | 67 |
| creator | Roh, Yi-Ju Chang, Dong-Jin Ryu, Seung-Tak |
| description | A SAR-assisted SAR ADC that uses a double clock-rate coarse decision technique is presented. The coarse ADC operates with a higher rate clock to reduce the MSBs decision time. The mismatch problem between coarse and fine ADCs is solved by using redundancy and background offset calibration. A simple metastability reduction technique for non-binary SAR ADC that does not require a lookup table is also proposed. The ADC core occupies a 0.0128-mm 2 area and consumes 1.9 mW under a 1-V supply. With an 80-MHz input, the ADC achieves an SNDR of 58.1 dB and an SFDR of 72.1 dB. The peak DNL and INL are 0.96 LSB and 1.6 LSB, respectively, and the figure of merit is 24.26 fJ/conversion-step. |
| doi_str_mv | 10.1109/TCSII.2020.2981971 |
| format | Article |
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The peak DNL and INL are 0.96 LSB and 1.6 LSB, respectively, and the figure of merit is 24.26 fJ/conversion-step.</description><subject>Calibration</subject><subject>Capacitors</subject><subject>Clocks</subject><subject>CMOS</subject><subject>Error correction</subject><subject>Figure of merit</subject><subject>Lookup tables</subject><subject>metastable error correction method</subject><subject>nonbinary SAR ADC</subject><subject>Redundancy</subject><subject>SAR-assisted SAR ADC</subject><subject>subranging SAR ADC</subject><subject>Switches</subject><subject>Timing</subject><issn>1549-7747</issn><issn>1558-3791</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kM1OwzAQhC0EEqXwAnCxxNmt13Hi-Bil_FRqqdQUcbRsxxUpbVzi5MDbk9CKw2p3pJld7YfQPdAJAJXTTV7M5xNGGZ0wmYIUcIFGEMcpiYSEy2HmkgjBxTW6CWFHKZM0YiOkMswpqQ84X64KDMz0RcmymAb85mtT1br5wUW2JlkIVWhdOQiczXL8UbWfeOY7s3c433v7Rda67Uevm-DwzNkqVL6-RVdbvQ_u7tzH6P35aZO_ksXqZZ5nC2KZjFtihWSmlBE3qYZt6aCXmptSW-q0tVQmwlpDwUQsBs4tc5CUVsdUJ0ZGIKIxejztPTb-u3OhVTvfNXV_UjGexJxLnqa9i51ctvEhNG6rjk116F9UQNUAUv2BVANIdQbZhx5Ooco59x-QlLNUiOgXNQJrSA</recordid><startdate>20201201</startdate><enddate>20201201</enddate><creator>Roh, Yi-Ju</creator><creator>Chang, Dong-Jin</creator><creator>Ryu, Seung-Tak</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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II, Express briefs</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Roh, Yi-Ju</au><au>Chang, Dong-Jin</au><au>Ryu, Seung-Tak</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC With Double Clock-Rate Coarse Decision</atitle><jtitle>IEEE transactions on circuits and systems. II, Express briefs</jtitle><stitle>TCSII</stitle><date>2020-12-01</date><risdate>2020</risdate><volume>67</volume><issue>12</issue><spage>2833</spage><epage>2837</epage><pages>2833-2837</pages><issn>1549-7747</issn><eissn>1558-3791</eissn><coden>ICSPE5</coden><abstract>A SAR-assisted SAR ADC that uses a double clock-rate coarse decision technique is presented. The coarse ADC operates with a higher rate clock to reduce the MSBs decision time. The mismatch problem between coarse and fine ADCs is solved by using redundancy and background offset calibration. A simple metastability reduction technique for non-binary SAR ADC that does not require a lookup table is also proposed. The ADC core occupies a 0.0128-mm 2 area and consumes 1.9 mW under a 1-V supply. With an 80-MHz input, the ADC achieves an SNDR of 58.1 dB and an SFDR of 72.1 dB. The peak DNL and INL are 0.96 LSB and 1.6 LSB, respectively, and the figure of merit is 24.26 fJ/conversion-step.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCSII.2020.2981971</doi><tpages>5</tpages><orcidid>https://orcid.org/0000-0002-6947-7785</orcidid><orcidid>https://orcid.org/0000-0002-0352-9407</orcidid></addata></record> |
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| subjects | Calibration Capacitors Clocks CMOS Error correction Figure of merit Lookup tables metastable error correction method nonbinary SAR ADC Redundancy SAR-assisted SAR ADC subranging SAR ADC Switches Timing |
| title | A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC With Double Clock-Rate Coarse Decision |
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