The Deep Learning Compiler: A Comprehensive Survey
The difficulty of deploying various deep learning (DL) models on diverse DL hardware has boosted the research and development of DL compilers in the community. Several DL compilers have been proposed from both industry and academia such as Tensorflow XLA and TVM. Similarly, the DL compilers take the...
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| Veröffentlicht in: | IEEE transactions on parallel and distributed systems 2021-03, Vol.32 (3), p.708-727 |
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| container_title | IEEE transactions on parallel and distributed systems |
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| creator | Li, Mingzhen Liu, Yi Liu, Xiaoyan Sun, Qingxiao You, Xin Yang, Hailong Luan, Zhongzhi Gan, Lin Yang, Guangwen Qian, Depei |
| description | The difficulty of deploying various deep learning (DL) models on diverse DL hardware has boosted the research and development of DL compilers in the community. Several DL compilers have been proposed from both industry and academia such as Tensorflow XLA and TVM. Similarly, the DL compilers take the DL models described in different DL frameworks as input, and then generate optimized codes for diverse DL hardware as output. However, none of the existing survey has analyzed the unique design architecture of the DL compilers comprehensively. In this article, we perform a comprehensive survey of existing DL compilers by dissecting the commonly adopted design in details, with emphasis on the DL oriented multi-level IRs, and frontend/backend optimizations. We present detailed analysis on the design of multi-level IRs and illustrate the commonly adopted optimization techniques. Finally, several insights are highlighted as the potential research directions of DL compiler. This is the first survey article focusing on the design architecture of DL compilers, which we hope can pave the road for future research towards DL compiler. |
| doi_str_mv | 10.1109/TPDS.2020.3030548 |
| format | Article |
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Several DL compilers have been proposed from both industry and academia such as Tensorflow XLA and TVM. Similarly, the DL compilers take the DL models described in different DL frameworks as input, and then generate optimized codes for diverse DL hardware as output. However, none of the existing survey has analyzed the unique design architecture of the DL compilers comprehensively. In this article, we perform a comprehensive survey of existing DL compilers by dissecting the commonly adopted design in details, with emphasis on the DL oriented multi-level IRs, and frontend/backend optimizations. We present detailed analysis on the design of multi-level IRs and illustrate the commonly adopted optimization techniques. Finally, several insights are highlighted as the potential research directions of DL compiler. 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| subjects | compiler Compilers Computational modeling Computer architecture Deep learning Design analysis Hardware Integrated circuit modeling intermediate representation Libraries Neural networks Optimization Optimization techniques R&D Research & development |
| title | The Deep Learning Compiler: A Comprehensive Survey |
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