AnyHLS: High-Level Synthesis With Partial Evaluation

Field programmable gate arrays (FPGAs) excel in low power and high throughput computations, but they are challenging to program. Traditionally, developers rely on hardware description languages, such as Verilog or VHDL to specify the hardware behavior at the register-transfer level. High-level synth...

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Veröffentlicht in:IEEE transactions on computer-aided design of integrated circuits and systems 2020-11, Vol.39 (11), p.3202-3214
Hauptverfasser: Ozkan, M. Akif, Perard-Gayot, Arsene, Membarth, Richard, Slusallek, Philipp, Leisa, Roland, Hack, Sebastian, Teich, Jurgen, Hannig, Frank
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Sprache:eng
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