Implementation of fast independent component analysis on field‐programmable gate array for resolving the slot collision issue in the space‐based automatic identification system

Summary The space‐based automatic identification system (S‐AIS) is a maritime safety and vessel monitoring system used to broadcast the ship position and other telemetry every few seconds in short bursts. A satellite‐based AIS receiver is of interest to defense community as it provides global or wide‐area coverage. However, when the satellite passes regions with elevated traffic density, a major challenge is to overcome the message or signal interference at the satellite receiver. This paper mainly focuses on developing a novel AIS satellite receiver that uses fast independent component analysis (FastICA) blind source separation technique to resolve the overlapped signals at the satellite. We propose an architecture to realize FastICA algorithm on hardware. In addition to this, we present Gaussian minimum shift keying modulator and demodulator design schemes used by the S‐AIS transponders. The proposed framework is realized on Virtex5‐xc5vlx110t field‐programmable gate array. The results obtained validate the effectiveness of the FastICA architecture realized by recovering the original ship data from the overlapped signals. Space‐based AIS receiver typically receives signals from a large number of Self‐Organized Time‐Division Multiple Access (SOTDMA) cells and in the regions of elevated traffic density, the organized structure is lost resulting in messages collisions at the satellite receiver. In this paper, we try to address this issue by proposing a novel AIS satellite receiver architecture based on the FastICA algorithm. The proposed framework was successfully implemented on Field programmable gate array (FPGA) to effectively decode the original message from the overlapping signals.