LOOPLock: Logic Optimization-Based Cyclic Logic Locking
SAT Attack, CycSAT, and Removal Attack have demonstrated their abilities to break most existing logic locking methods. In this article, we propose a new cyclic logic locking method to invalidate these attacks simultaneously. Our main intention is to create noncombinational cycles to lock a circuit....
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| Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 2020-10, Vol.39 (10), p.2178-2191 |
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| container_title | IEEE transactions on computer-aided design of integrated circuits and systems |
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| creator | Chiang, Hsiao-Yu Chen, Yung-Chih Ji, De-Xuan Yang, Xiang-Min Lin, Chia-Chun Wang, Chun-Yao |
| description | SAT Attack, CycSAT, and Removal Attack have demonstrated their abilities to break most existing logic locking methods. In this article, we propose a new cyclic logic locking method to invalidate these attacks simultaneously. Our main intention is to create noncombinational cycles to lock a circuit. Specifically, the noncombinational behavior in the noncombinational cycles that is unobservable at the primary outputs (POs) needs to be preserved when the correct key-vector is fed to resist CycSAT, and the noncombinational behavior in the noncombinational cycles affecting POs needs to be preserved when the incorrect key-vector is fed to invalidate SAT Attack. Furthermore, some nodes will be removed when applying our locking method, which is able to defend Removal Attack. The experimental results show the effectiveness and low area overhead of the proposed method. |
| doi_str_mv | 10.1109/TCAD.2019.2960351 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_journals_2446058659</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>8935307</ieee_id><sourcerecordid>2446058659</sourcerecordid><originalsourceid>FETCH-LOGICAL-c359t-e9d3d63731f03d9fe6998e6b30c2ff92871f930af2c3c1ac786ce329c5c7aad33</originalsourceid><addsrcrecordid>eNo9kMtOwzAQRS0EEqXwAYhNJdYpY08cZ9iV8JQihUVZW8axK5e2KXFYlK8nUSpWs7jn3pEOY9cc5pwD3S2LxeNcAKe5oAxQ8hM24YQqSbnkp2wCQuUJgIJzdhHjGoCnUtCEqbKq3svGft3PymYV7Kzad2Ebfk0Xml3yYKKrZ8XBbvpkzAc27FaX7MybTXRXxztlH89Py-I1KauXt2JRJhYldYmjGusMFXIPWJN3GVHusk8EK7wnkSvuCcF4YdFyY1WeWYeCrLTKmBpxym7H3X3bfP-42Ol189Pu-pdapGkGMs8k9RQfKds2MbbO630btqY9aA568KMHP3rwo49--s7N2AnOuX8-J5QICv8AaVFfcg</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2446058659</pqid></control><display><type>article</type><title>LOOPLock: Logic Optimization-Based Cyclic Logic Locking</title><source>IEEE Electronic Library (IEL)</source><creator>Chiang, Hsiao-Yu ; Chen, Yung-Chih ; Ji, De-Xuan ; Yang, Xiang-Min ; Lin, Chia-Chun ; Wang, Chun-Yao</creator><creatorcontrib>Chiang, Hsiao-Yu ; Chen, Yung-Chih ; Ji, De-Xuan ; Yang, Xiang-Min ; Lin, Chia-Chun ; Wang, Chun-Yao</creatorcontrib><description>SAT Attack, CycSAT, and Removal Attack have demonstrated their abilities to break most existing logic locking methods. In this article, we propose a new cyclic logic locking method to invalidate these attacks simultaneously. Our main intention is to create noncombinational cycles to lock a circuit. Specifically, the noncombinational behavior in the noncombinational cycles that is unobservable at the primary outputs (POs) needs to be preserved when the correct key-vector is fed to resist CycSAT, and the noncombinational behavior in the noncombinational cycles affecting POs needs to be preserved when the incorrect key-vector is fed to invalidate SAT Attack. Furthermore, some nodes will be removed when applying our locking method, which is able to defend Removal Attack. The experimental results show the effectiveness and low area overhead of the proposed method.</description><identifier>ISSN: 0278-0070</identifier><identifier>EISSN: 1937-4151</identifier><identifier>DOI: 10.1109/TCAD.2019.2960351</identifier><identifier>CODEN: ITCSDI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Circuits ; Cyclic logic locking ; CycSAT ; Delays ; Electronics packaging ; hardware security ; Integrated circuits ; Inverters ; Locking ; Logic ; Logic gates ; logic optimization ; Optimization ; SAT Attack ; Security</subject><ispartof>IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.2178-2191</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2020</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c359t-e9d3d63731f03d9fe6998e6b30c2ff92871f930af2c3c1ac786ce329c5c7aad33</citedby><cites>FETCH-LOGICAL-c359t-e9d3d63731f03d9fe6998e6b30c2ff92871f930af2c3c1ac786ce329c5c7aad33</cites><orcidid>0000-0001-7194-5878 ; 0000-0002-3934-800X ; 0000-0002-0136-9825 ; 0000-0002-3732-1807</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8935307$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,778,782,794,27911,27912,54745</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8935307$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Chiang, Hsiao-Yu</creatorcontrib><creatorcontrib>Chen, Yung-Chih</creatorcontrib><creatorcontrib>Ji, De-Xuan</creatorcontrib><creatorcontrib>Yang, Xiang-Min</creatorcontrib><creatorcontrib>Lin, Chia-Chun</creatorcontrib><creatorcontrib>Wang, Chun-Yao</creatorcontrib><title>LOOPLock: Logic Optimization-Based Cyclic Logic Locking</title><title>IEEE transactions on computer-aided design of integrated circuits and systems</title><addtitle>TCAD</addtitle><description>SAT Attack, CycSAT, and Removal Attack have demonstrated their abilities to break most existing logic locking methods. In this article, we propose a new cyclic logic locking method to invalidate these attacks simultaneously. Our main intention is to create noncombinational cycles to lock a circuit. Specifically, the noncombinational behavior in the noncombinational cycles that is unobservable at the primary outputs (POs) needs to be preserved when the correct key-vector is fed to resist CycSAT, and the noncombinational behavior in the noncombinational cycles affecting POs needs to be preserved when the incorrect key-vector is fed to invalidate SAT Attack. Furthermore, some nodes will be removed when applying our locking method, which is able to defend Removal Attack. The experimental results show the effectiveness and low area overhead of the proposed method.</description><subject>Circuits</subject><subject>Cyclic logic locking</subject><subject>CycSAT</subject><subject>Delays</subject><subject>Electronics packaging</subject><subject>hardware security</subject><subject>Integrated circuits</subject><subject>Inverters</subject><subject>Locking</subject><subject>Logic</subject><subject>Logic gates</subject><subject>logic optimization</subject><subject>Optimization</subject><subject>SAT Attack</subject><subject>Security</subject><issn>0278-0070</issn><issn>1937-4151</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kMtOwzAQRS0EEqXwAYhNJdYpY08cZ9iV8JQihUVZW8axK5e2KXFYlK8nUSpWs7jn3pEOY9cc5pwD3S2LxeNcAKe5oAxQ8hM24YQqSbnkp2wCQuUJgIJzdhHjGoCnUtCEqbKq3svGft3PymYV7Kzad2Ebfk0Xml3yYKKrZ8XBbvpkzAc27FaX7MybTXRXxztlH89Py-I1KauXt2JRJhYldYmjGusMFXIPWJN3GVHusk8EK7wnkSvuCcF4YdFyY1WeWYeCrLTKmBpxym7H3X3bfP-42Ol189Pu-pdapGkGMs8k9RQfKds2MbbO630btqY9aA568KMHP3rwo49--s7N2AnOuX8-J5QICv8AaVFfcg</recordid><startdate>20201001</startdate><enddate>20201001</enddate><creator>Chiang, Hsiao-Yu</creator><creator>Chen, Yung-Chih</creator><creator>Ji, De-Xuan</creator><creator>Yang, Xiang-Min</creator><creator>Lin, Chia-Chun</creator><creator>Wang, Chun-Yao</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><orcidid>https://orcid.org/0000-0001-7194-5878</orcidid><orcidid>https://orcid.org/0000-0002-3934-800X</orcidid><orcidid>https://orcid.org/0000-0002-0136-9825</orcidid><orcidid>https://orcid.org/0000-0002-3732-1807</orcidid></search><sort><creationdate>20201001</creationdate><title>LOOPLock: Logic Optimization-Based Cyclic Logic Locking</title><author>Chiang, Hsiao-Yu ; Chen, Yung-Chih ; Ji, De-Xuan ; Yang, Xiang-Min ; Lin, Chia-Chun ; Wang, Chun-Yao</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c359t-e9d3d63731f03d9fe6998e6b30c2ff92871f930af2c3c1ac786ce329c5c7aad33</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2020</creationdate><topic>Circuits</topic><topic>Cyclic logic locking</topic><topic>CycSAT</topic><topic>Delays</topic><topic>Electronics packaging</topic><topic>hardware security</topic><topic>Integrated circuits</topic><topic>Inverters</topic><topic>Locking</topic><topic>Logic</topic><topic>Logic gates</topic><topic>logic optimization</topic><topic>Optimization</topic><topic>SAT Attack</topic><topic>Security</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Chiang, Hsiao-Yu</creatorcontrib><creatorcontrib>Chen, Yung-Chih</creatorcontrib><creatorcontrib>Ji, De-Xuan</creatorcontrib><creatorcontrib>Yang, Xiang-Min</creatorcontrib><creatorcontrib>Lin, Chia-Chun</creatorcontrib><creatorcontrib>Wang, Chun-Yao</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chiang, Hsiao-Yu</au><au>Chen, Yung-Chih</au><au>Ji, De-Xuan</au><au>Yang, Xiang-Min</au><au>Lin, Chia-Chun</au><au>Wang, Chun-Yao</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>LOOPLock: Logic Optimization-Based Cyclic Logic Locking</atitle><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle><stitle>TCAD</stitle><date>2020-10-01</date><risdate>2020</risdate><volume>39</volume><issue>10</issue><spage>2178</spage><epage>2191</epage><pages>2178-2191</pages><issn>0278-0070</issn><eissn>1937-4151</eissn><coden>ITCSDI</coden><abstract>SAT Attack, CycSAT, and Removal Attack have demonstrated their abilities to break most existing logic locking methods. In this article, we propose a new cyclic logic locking method to invalidate these attacks simultaneously. Our main intention is to create noncombinational cycles to lock a circuit. Specifically, the noncombinational behavior in the noncombinational cycles that is unobservable at the primary outputs (POs) needs to be preserved when the correct key-vector is fed to resist CycSAT, and the noncombinational behavior in the noncombinational cycles affecting POs needs to be preserved when the incorrect key-vector is fed to invalidate SAT Attack. Furthermore, some nodes will be removed when applying our locking method, which is able to defend Removal Attack. The experimental results show the effectiveness and low area overhead of the proposed method.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCAD.2019.2960351</doi><tpages>14</tpages><orcidid>https://orcid.org/0000-0001-7194-5878</orcidid><orcidid>https://orcid.org/0000-0002-3934-800X</orcidid><orcidid>https://orcid.org/0000-0002-0136-9825</orcidid><orcidid>https://orcid.org/0000-0002-3732-1807</orcidid></addata></record> |
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| source | IEEE Electronic Library (IEL) |
| subjects | Circuits Cyclic logic locking CycSAT Delays Electronics packaging hardware security Integrated circuits Inverters Locking Logic Logic gates logic optimization Optimization SAT Attack Security |
| title | LOOPLock: Logic Optimization-Based Cyclic Logic Locking |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-16T03%3A15%3A46IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=LOOPLock:%20Logic%20Optimization-Based%20Cyclic%20Logic%20Locking&rft.jtitle=IEEE%20transactions%20on%20computer-aided%20design%20of%20integrated%20circuits%20and%20systems&rft.au=Chiang,%20Hsiao-Yu&rft.date=2020-10-01&rft.volume=39&rft.issue=10&rft.spage=2178&rft.epage=2191&rft.pages=2178-2191&rft.issn=0278-0070&rft.eissn=1937-4151&rft.coden=ITCSDI&rft_id=info:doi/10.1109/TCAD.2019.2960351&rft_dat=%3Cproquest_RIE%3E2446058659%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2446058659&rft_id=info:pmid/&rft_ieee_id=8935307&rfr_iscdi=true |