LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults
Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the quality of through-silicon vias (TSVs) varies during the fabrication and bonding process. If one TSV exhibits a defect during its manufacturing process, the probability of multiple defects occurring in the...
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Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 2020-10, Vol.39 (10), p.2938-2951 |
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creator | Ni, Tianming Yao, Yao Chang, Hao Lu, Lin Liang, Huaguo Yan, Aibin Huang, Zhengfeng Wen, Xiaoqing |
description | Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the quality of through-silicon vias (TSVs) varies during the fabrication and bonding process. If one TSV exhibits a defect during its manufacturing process, the probability of multiple defects occurring in the TSVs neighboring the faulty TSV increases, i.e., the TSV defects tend to be clustered, which significantly reduces the yield of 3-D integrated circuit. To resolve the clustered TSV faults, router-based, ring-based, group-based, and cellular-based redundant TSV (RTSV) architectures were proposed. However, the repair rate is low and the hardware overhead as well as delay overhead is high. In this article, we propose a honeycomb-based RTSV architecture to utilize the area and delay more efficiently as well as to maintain high yield. The simulation results show that the proposed architecture has a 99.84% repair rate for uniform faults and an 81.42% repair rate for highly clustered faults. The proposed design achieves a 51.66% reduction of hardware overhead compared with the router-based design and a 20.69%, 46.93%, 34.17%, and 11.15% reduction of total delay compared with ring-based, router-based, group-based, and cellular-based methods, respectively. |
doi_str_mv | 10.1109/TCAD.2019.2946243 |
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If one TSV exhibits a defect during its manufacturing process, the probability of multiple defects occurring in the TSVs neighboring the faulty TSV increases, i.e., the TSV defects tend to be clustered, which significantly reduces the yield of 3-D integrated circuit. To resolve the clustered TSV faults, router-based, ring-based, group-based, and cellular-based redundant TSV (RTSV) architectures were proposed. However, the repair rate is low and the hardware overhead as well as delay overhead is high. In this article, we propose a honeycomb-based RTSV architecture to utilize the area and delay more efficiently as well as to maintain high yield. The simulation results show that the proposed architecture has a 99.84% repair rate for uniform faults and an 81.42% repair rate for highly clustered faults. The proposed design achieves a 51.66% reduction of hardware overhead compared with the router-based design and a 20.69%, 46.93%, 34.17%, and 11.15% reduction of total delay compared with ring-based, router-based, group-based, and cellular-based methods, respectively.</description><identifier>ISSN: 0278-0070</identifier><identifier>EISSN: 1937-4151</identifier><identifier>DOI: 10.1109/TCAD.2019.2946243</identifier><identifier>CODEN: ITCSDI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>3-D integrated circuits (3D-ICs) ; Architecture ; Circuit faults ; clustered faults ; Computer architecture ; Defects ; Delay ; Delays ; Faults ; Hardware ; Integrated circuits ; Interconnections ; Maintenance engineering ; Redundancy ; redundancy architecture ; Repair ; Rings (mathematics) ; Surface roughness ; Through-silicon vias ; through-silicon vias (TSVs) ; yield</subject><ispartof>IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.2938-2951</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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The proposed design achieves a 51.66% reduction of hardware overhead compared with the router-based design and a 20.69%, 46.93%, 34.17%, and 11.15% reduction of total delay compared with ring-based, router-based, group-based, and cellular-based methods, respectively.</description><subject>3-D integrated circuits (3D-ICs)</subject><subject>Architecture</subject><subject>Circuit faults</subject><subject>clustered faults</subject><subject>Computer architecture</subject><subject>Defects</subject><subject>Delay</subject><subject>Delays</subject><subject>Faults</subject><subject>Hardware</subject><subject>Integrated circuits</subject><subject>Interconnections</subject><subject>Maintenance engineering</subject><subject>Redundancy</subject><subject>redundancy architecture</subject><subject>Repair</subject><subject>Rings (mathematics)</subject><subject>Surface roughness</subject><subject>Through-silicon vias</subject><subject>through-silicon vias (TSVs)</subject><subject>yield</subject><issn>0278-0070</issn><issn>1937-4151</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kE1Lw0AQQBdRsFZ_gHhZ8Jy638l6q9FaISjU6jVsNhObkmbrbqL035vS4mkO894MPISuKZlQSvTdMp0-ThihesK0UEzwEzSimseRoJKeohFhcRIREpNzdBHCmhAqJNMj5LJ0voiW75_3-NX9QIMz94tTFzps2hLP669Vs8ML2Jram6IBPHct7KzbFNGDCVDiwRzWZd-WprU7PPV2VXdgu94DrpzHadOHDvxAzkzfdOESnVWmCXB1nGP0MXtapvMoe3t-SadZZLnUXaSUTQQzVOnScq0VLZSiYLiQmks2MCWxghdlVXDFOAEli0rqJKYxlUCU4WN0e7i79e67h9Dla9f7dniZMyEUkYmkfKDogbLeheChyre-3hi_yynJ913zfdd83zU_dh2cm4NTA8A_nySKJYrzPyhCciw</recordid><startdate>20201001</startdate><enddate>20201001</enddate><creator>Ni, Tianming</creator><creator>Yao, Yao</creator><creator>Chang, Hao</creator><creator>Lu, Lin</creator><creator>Liang, Huaguo</creator><creator>Yan, Aibin</creator><creator>Huang, Zhengfeng</creator><creator>Wen, Xiaoqing</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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If one TSV exhibits a defect during its manufacturing process, the probability of multiple defects occurring in the TSVs neighboring the faulty TSV increases, i.e., the TSV defects tend to be clustered, which significantly reduces the yield of 3-D integrated circuit. To resolve the clustered TSV faults, router-based, ring-based, group-based, and cellular-based redundant TSV (RTSV) architectures were proposed. However, the repair rate is low and the hardware overhead as well as delay overhead is high. In this article, we propose a honeycomb-based RTSV architecture to utilize the area and delay more efficiently as well as to maintain high yield. The simulation results show that the proposed architecture has a 99.84% repair rate for uniform faults and an 81.42% repair rate for highly clustered faults. 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subjects | 3-D integrated circuits (3D-ICs) Architecture Circuit faults clustered faults Computer architecture Defects Delay Delays Faults Hardware Integrated circuits Interconnections Maintenance engineering Redundancy redundancy architecture Repair Rings (mathematics) Surface roughness Through-silicon vias through-silicon vias (TSVs) yield |
title | LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults |
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