A modular Vedic multiplier architecture for model-based design and deployment on FPGA platforms

Multiplication is a fundamental operation in most signal and image processing applications. In this paper, a new architecture for a Vedic multiplier implementing ‘Urdhava-tiryakbhyam’ methodology is proposed. The presented architecture is completely modular and is conceived to be implemented in mode...

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Veröffentlicht in:	Microprocessors and microsystems 2020-07, Vol.76, p.103106, Article 103106
Hauptverfasser:	Bianchi, Valentina, De Munari, Ilaria
Format:	Artikel
Sprache:	eng
Schlagworte:	Architecture Field programmable gate arrays FPGA Hardware description languages HDL code Image processing Integrated circuits Model-based design Multiplication Multiplier Occupancy Signal processing Simulink VHSIC (circuits)
Online-Zugang:	Volltext
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