IC Random Number Generator Exploiting Two Simultaneous Metastable Events of Tetrahedral Oscillators

A low-cost random number generator (RNG) based on a tetrahedral ring oscillator, which can be utilized in cryptographic systems, is presented. The proposed design exploits two metastable events in the oscillator caused by turning on and off three additional inverters in the classical tetrahedral oscillator, which improves entropy. The design is implemented on FPGA as a proof of concept, but the ASIC implementation will be carried out in the future. A method has been devised to implement this circuit on FPGA. Techniques to increase randomness have been used, such as adjusting the sampling signal considering 1 and 0 balance of the output. The proposed design is compared with the classical tetrahedral oscillator based RNG, and it is observed to be better. The RNG is tested with the National Institute of Standard and Technology (NIST) test suite to prove randomness. The design occupies an area of 0.0036mm 2 with a power consumption of 200mW and a bit rate of 10Mb/s. The number of oscillators has been dropped by 60% compared to the classical method.