Radiation-Hardened, Read-Disturbance-Free New-Quatro-10T Memory Cell for Aerospace Applications
Soft error protection is a paramount requirement for memories exposed to radiation environment. To satisfy the demand, a radiation-hardened new-quatro 10T memory cell is proposed in this brief, which is immune to single-node upset and also has high resilience to multinode upset while features read-d...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2020-08, Vol.28 (8), p.1935-1939 |
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| container_end_page | 1939 |
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| container_issue | 8 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
| container_volume | 28 |
| creator | Wen, Liang Zhang, Yuejun Wang, Pengjun |
| description | Soft error protection is a paramount requirement for memories exposed to radiation environment. To satisfy the demand, a radiation-hardened new-quatro 10T memory cell is proposed in this brief, which is immune to single-node upset and also has high resilience to multinode upset while features read-disturbance-free benefiting from its internal quad-node interlocked feedback mechanism. Simulation results show that it provides ample radiation robustness to single event and gives 1.75\times improvements in multinode upset tolerance when compared with the previous 12T dual-interlocked storage cell (DICE-12T) bitcell, signifying the higher fault tolerance capability. In addition, the proposed design also achieves 6.48\times enhancement in read noise margin when compared with the DICE-12T bitcell while compromising only 2.1\times larger area than a reference 6T cell based on a 65-nm logic design rule, exhibiting the superiority in read stability. |
| doi_str_mv | 10.1109/TVLSI.2020.2991755 |
| format | Article |
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To satisfy the demand, a radiation-hardened new-quatro 10T memory cell is proposed in this brief, which is immune to single-node upset and also has high resilience to multinode upset while features read-disturbance-free benefiting from its internal quad-node interlocked feedback mechanism. Simulation results show that it provides ample radiation robustness to single event and gives <inline-formula> <tex-math notation="LaTeX">1.75\times </tex-math></inline-formula> improvements in multinode upset tolerance when compared with the previous 12T dual-interlocked storage cell (DICE-12T) bitcell, signifying the higher fault tolerance capability. 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(IEEE) 2020</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c361t-798b66110e46f43c4a00339bf86d7b3d6787de13d1e095adaf0e1930545a9bc53</citedby><cites>FETCH-LOGICAL-c361t-798b66110e46f43c4a00339bf86d7b3d6787de13d1e095adaf0e1930545a9bc53</cites><orcidid>0000-0002-1461-3719 ; 0000-0003-1132-6332 ; 0000-0001-5490-4943</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9093898$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9093898$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Wen, Liang</creatorcontrib><creatorcontrib>Zhang, Yuejun</creatorcontrib><creatorcontrib>Wang, Pengjun</creatorcontrib><title>Radiation-Hardened, Read-Disturbance-Free New-Quatro-10T Memory Cell for Aerospace Applications</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description><![CDATA[Soft error protection is a paramount requirement for memories exposed to radiation environment. To satisfy the demand, a radiation-hardened new-quatro 10T memory cell is proposed in this brief, which is immune to single-node upset and also has high resilience to multinode upset while features read-disturbance-free benefiting from its internal quad-node interlocked feedback mechanism. Simulation results show that it provides ample radiation robustness to single event and gives <inline-formula> <tex-math notation="LaTeX">1.75\times </tex-math></inline-formula> improvements in multinode upset tolerance when compared with the previous 12T dual-interlocked storage cell (DICE-12T) bitcell, signifying the higher fault tolerance capability. In addition, the proposed design also achieves <inline-formula> <tex-math notation="LaTeX">6.48\times </tex-math></inline-formula> enhancement in read noise margin when compared with the DICE-12T bitcell while compromising only <inline-formula> <tex-math notation="LaTeX">2.1\times </tex-math></inline-formula> larger area than a reference 6T cell based on a 65-nm logic design rule, exhibiting the superiority in read stability.]]></description><subject>Aerospace</subject><subject>Fault tolerance</subject><subject>Feedback loop</subject><subject>Logic design</subject><subject>memory</subject><subject>MOS devices</subject><subject>quarto</subject><subject>Radiation hardening</subject><subject>radiation-hardened</subject><subject>Random access memory</subject><subject>read-disturbance-free</subject><subject>Resilience</subject><subject>Robustness</subject><subject>Single event upsets</subject><subject>single-event upset (SEU)</subject><subject>soft error</subject><subject>Soft errors</subject><subject>Transient analysis</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kMtOwzAQRSMEEqXwA7CJxBaX8SuJl1WhtFIBUQpby4knUqo2CXYi1L_HfYjZzCzuvTNzouiWwohSUI-r78XnfMSAwYgpRVMpz6IBlTIlKtR5mCHhJGMULqMr79cAVAgFg0gvja1MVzU1mRlnsUb7EC_RWPJU-a53uakLJFOHGL_hL_noTecaQmEVv-K2cbt4gptNXDYuHqNrfGsKjMdtu6mKQ6i_ji5Ks_F4c-rD6Gv6vJrMyOL9ZT4ZL0jBE9qRVGV5koRXUCSl4IUwAJyrvMwSm-bcJmmWWqTcUgQljTUlIFUcpJBG5YXkw-j-mNu65qdH3-l107s6rNRMsKBkXIigYkdVEW71Dkvdumpr3E5T0HuQ-gBS70HqE8hgujuaKkT8NyhQPFMZ_wMir25C</recordid><startdate>20200801</startdate><enddate>20200801</enddate><creator>Wen, Liang</creator><creator>Zhang, Yuejun</creator><creator>Wang, Pengjun</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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To satisfy the demand, a radiation-hardened new-quatro 10T memory cell is proposed in this brief, which is immune to single-node upset and also has high resilience to multinode upset while features read-disturbance-free benefiting from its internal quad-node interlocked feedback mechanism. Simulation results show that it provides ample radiation robustness to single event and gives <inline-formula> <tex-math notation="LaTeX">1.75\times </tex-math></inline-formula> improvements in multinode upset tolerance when compared with the previous 12T dual-interlocked storage cell (DICE-12T) bitcell, signifying the higher fault tolerance capability. In addition, the proposed design also achieves <inline-formula> <tex-math notation="LaTeX">6.48\times </tex-math></inline-formula> enhancement in read noise margin when compared with the DICE-12T bitcell while compromising only <inline-formula> <tex-math notation="LaTeX">2.1\times </tex-math></inline-formula> larger area than a reference 6T cell based on a 65-nm logic design rule, exhibiting the superiority in read stability.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2020.2991755</doi><tpages>5</tpages><orcidid>https://orcid.org/0000-0002-1461-3719</orcidid><orcidid>https://orcid.org/0000-0003-1132-6332</orcidid><orcidid>https://orcid.org/0000-0001-5490-4943</orcidid></addata></record> |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Aerospace Fault tolerance Feedback loop Logic design memory MOS devices quarto Radiation hardening radiation-hardened Random access memory read-disturbance-free Resilience Robustness Single event upsets single-event upset (SEU) soft error Soft errors Transient analysis |
| title | Radiation-Hardened, Read-Disturbance-Free New-Quatro-10T Memory Cell for Aerospace Applications |
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