Input bias current reduction technique for operational amplifier in a standard CMOS technology
This paper presents input bias current (Ibias) reduction technique for high impedance CMOS op‐amps with the proposed current compensation circuit to deal with the leakage current caused by Electro‐Static Discharge (ESD) protection circuit of the IC. High input impedance CMOS op‐amps are widely used...
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| Veröffentlicht in: | Electronics and communications in Japan 2020-07, Vol.103 (7), p.30-36 |
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| container_end_page | 36 |
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| container_issue | 7 |
| container_start_page | 30 |
| container_title | Electronics and communications in Japan |
| container_volume | 103 |
| creator | Chin, Koken Ohsawa, Mamoru Kitajima, Atsushi Arai, Yoshiaki Yamashita, Jun Ito, Hisashi San, Hao |
| description | This paper presents input bias current (Ibias) reduction technique for high impedance CMOS op‐amps with the proposed current compensation circuit to deal with the leakage current caused by Electro‐Static Discharge (ESD) protection circuit of the IC. High input impedance CMOS op‐amps are widely used for the application of high precision sensors with quite small input current. However, the leakage current of ESD protection circuit for op‐amp causes a nonideality error of the Ibias. Especially, the ESD leakage current increases drastically at the high temperature environment, and hence the Ibias of CMOS op‐amp also increased significantly. An ESD leakage current compensation circuit is introduced to reduce the Ibias of CMOS op‐amp. The prototype amplifier with the proposed current compensation circuit is designed and fabricated in standard 0.7 µm CMOS technology. Measurement results show that the Ibias is reduced to a 100 pA or less from a typical 2.3 nA at 150°C. |
| doi_str_mv | 10.1002/ecj.12242 |
| format | Article |
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High input impedance CMOS op‐amps are widely used for the application of high precision sensors with quite small input current. However, the leakage current of ESD protection circuit for op‐amp causes a nonideality error of the Ibias. Especially, the ESD leakage current increases drastically at the high temperature environment, and hence the Ibias of CMOS op‐amp also increased significantly. An ESD leakage current compensation circuit is introduced to reduce the Ibias of CMOS op‐amp. The prototype amplifier with the proposed current compensation circuit is designed and fabricated in standard 0.7 µm CMOS technology. Measurement results show that the Ibias is reduced to a 100 pA or less from a typical 2.3 nA at 150°C.</description><identifier>ISSN: 1942-9533</identifier><identifier>EISSN: 1942-9541</identifier><identifier>DOI: 10.1002/ecj.12242</identifier><language>eng</language><publisher>Hoboken: Wiley Subscription Services, Inc</publisher><subject>Bias ; Circuit design ; Circuits ; CMOS ; CMOS op‐amp ; Compensation ; Electrostatic discharges ; ESD protection circuit ; High impedance ; High temperature environments ; input bias current ; Input impedance ; Integrated circuits ; Leakage current ; Operational amplifiers ; Reduction ; Static electricity</subject><ispartof>Electronics and communications in Japan, 2020-07, Vol.103 (7), p.30-36</ispartof><rights>2020 Wiley Periodicals LLC</rights><rights>2020 by Wiley Periodicals LLC</rights><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c3232-88a19a822c82fe776a7aece27c42d521eb8a8e28670825c57c4010d9c0f3c68a3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://onlinelibrary.wiley.com/doi/pdf/10.1002%2Fecj.12242$$EPDF$$P50$$Gwiley$$H</linktopdf><linktohtml>$$Uhttps://onlinelibrary.wiley.com/doi/full/10.1002%2Fecj.12242$$EHTML$$P50$$Gwiley$$H</linktohtml><link.rule.ids>314,780,784,1416,27923,27924,45573,45574</link.rule.ids></links><search><creatorcontrib>Chin, Koken</creatorcontrib><creatorcontrib>Ohsawa, Mamoru</creatorcontrib><creatorcontrib>Kitajima, Atsushi</creatorcontrib><creatorcontrib>Arai, Yoshiaki</creatorcontrib><creatorcontrib>Yamashita, Jun</creatorcontrib><creatorcontrib>Ito, Hisashi</creatorcontrib><creatorcontrib>San, Hao</creatorcontrib><title>Input bias current reduction technique for operational amplifier in a standard CMOS technology</title><title>Electronics and communications in Japan</title><description>This paper presents input bias current (Ibias) reduction technique for high impedance CMOS op‐amps with the proposed current compensation circuit to deal with the leakage current caused by Electro‐Static Discharge (ESD) protection circuit of the IC. High input impedance CMOS op‐amps are widely used for the application of high precision sensors with quite small input current. However, the leakage current of ESD protection circuit for op‐amp causes a nonideality error of the Ibias. Especially, the ESD leakage current increases drastically at the high temperature environment, and hence the Ibias of CMOS op‐amp also increased significantly. An ESD leakage current compensation circuit is introduced to reduce the Ibias of CMOS op‐amp. The prototype amplifier with the proposed current compensation circuit is designed and fabricated in standard 0.7 µm CMOS technology. Measurement results show that the Ibias is reduced to a 100 pA or less from a typical 2.3 nA at 150°C.</description><subject>Bias</subject><subject>Circuit design</subject><subject>Circuits</subject><subject>CMOS</subject><subject>CMOS op‐amp</subject><subject>Compensation</subject><subject>Electrostatic discharges</subject><subject>ESD protection circuit</subject><subject>High impedance</subject><subject>High temperature environments</subject><subject>input bias current</subject><subject>Input impedance</subject><subject>Integrated circuits</subject><subject>Leakage current</subject><subject>Operational amplifiers</subject><subject>Reduction</subject><subject>Static electricity</subject><issn>1942-9533</issn><issn>1942-9541</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><recordid>eNp1kM1OwzAQhC0EEqVw4A0sceKQ1l47iXNEVflTUQ_AFWvrOOAqjYOdCPXtSQnixmlHo29WoyHkkrMZZwzm1mxnHEDCEZnwQkJSpJIf_2khTslZjFvGMplKMSFvD03bd3TjMFLTh2CbjgZb9qZzvqGdNR-N--wtrXygvrUBDz7WFHdt7SpnA3UNRRo7bEoMJV08rZ_HmK_9-_6cnFRYR3vxe6fk9Xb5srhPVuu7h8XNKjECBCRKIS9QARgFlc3zDHO0xkJuJJQpcLtRqCyoLGcKUpMOPuOsLAyrhMkUiim5Gv-2wQ91Y6e3vg9D0ahBcsGlkoIN1PVImeBjDLbSbXA7DHvNmT7Mp4f59M98Azsf2S9X2_3_oF4uHsfEN4f1cTY</recordid><startdate>202007</startdate><enddate>202007</enddate><creator>Chin, Koken</creator><creator>Ohsawa, Mamoru</creator><creator>Kitajima, Atsushi</creator><creator>Arai, Yoshiaki</creator><creator>Yamashita, Jun</creator><creator>Ito, Hisashi</creator><creator>San, Hao</creator><general>Wiley Subscription Services, Inc</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>202007</creationdate><title>Input bias current reduction technique for operational amplifier in a standard CMOS technology</title><author>Chin, Koken ; Ohsawa, Mamoru ; Kitajima, Atsushi ; Arai, Yoshiaki ; Yamashita, Jun ; Ito, Hisashi ; San, Hao</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c3232-88a19a822c82fe776a7aece27c42d521eb8a8e28670825c57c4010d9c0f3c68a3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2020</creationdate><topic>Bias</topic><topic>Circuit design</topic><topic>Circuits</topic><topic>CMOS</topic><topic>CMOS op‐amp</topic><topic>Compensation</topic><topic>Electrostatic discharges</topic><topic>ESD protection circuit</topic><topic>High impedance</topic><topic>High temperature environments</topic><topic>input bias current</topic><topic>Input impedance</topic><topic>Integrated circuits</topic><topic>Leakage current</topic><topic>Operational amplifiers</topic><topic>Reduction</topic><topic>Static electricity</topic><toplevel>online_resources</toplevel><creatorcontrib>Chin, Koken</creatorcontrib><creatorcontrib>Ohsawa, Mamoru</creatorcontrib><creatorcontrib>Kitajima, Atsushi</creatorcontrib><creatorcontrib>Arai, Yoshiaki</creatorcontrib><creatorcontrib>Yamashita, Jun</creatorcontrib><creatorcontrib>Ito, Hisashi</creatorcontrib><creatorcontrib>San, Hao</creatorcontrib><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>Electronics and communications in Japan</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Chin, Koken</au><au>Ohsawa, Mamoru</au><au>Kitajima, Atsushi</au><au>Arai, Yoshiaki</au><au>Yamashita, Jun</au><au>Ito, Hisashi</au><au>San, Hao</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Input bias current reduction technique for operational amplifier in a standard CMOS technology</atitle><jtitle>Electronics and communications in Japan</jtitle><date>2020-07</date><risdate>2020</risdate><volume>103</volume><issue>7</issue><spage>30</spage><epage>36</epage><pages>30-36</pages><issn>1942-9533</issn><eissn>1942-9541</eissn><abstract>This paper presents input bias current (Ibias) reduction technique for high impedance CMOS op‐amps with the proposed current compensation circuit to deal with the leakage current caused by Electro‐Static Discharge (ESD) protection circuit of the IC. High input impedance CMOS op‐amps are widely used for the application of high precision sensors with quite small input current. However, the leakage current of ESD protection circuit for op‐amp causes a nonideality error of the Ibias. Especially, the ESD leakage current increases drastically at the high temperature environment, and hence the Ibias of CMOS op‐amp also increased significantly. An ESD leakage current compensation circuit is introduced to reduce the Ibias of CMOS op‐amp. The prototype amplifier with the proposed current compensation circuit is designed and fabricated in standard 0.7 µm CMOS technology. Measurement results show that the Ibias is reduced to a 100 pA or less from a typical 2.3 nA at 150°C.</abstract><cop>Hoboken</cop><pub>Wiley Subscription Services, Inc</pub><doi>10.1002/ecj.12242</doi><tpages>7</tpages></addata></record> |
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| subjects | Bias Circuit design Circuits CMOS CMOS op‐amp Compensation Electrostatic discharges ESD protection circuit High impedance High temperature environments input bias current Input impedance Integrated circuits Leakage current Operational amplifiers Reduction Static electricity |
| title | Input bias current reduction technique for operational amplifier in a standard CMOS technology |
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