A Dead-Zone-Free Zero Blind-Zone High-Speed Phase Frequency Detector for Charge-Pump PLL

This paper presents a novel architecture for phase frequency detector (PFD) which eliminates the blind zone effect as well as the dead zone for a charge-pump phase-locked loop (CP-PLL). This PFD is designed in 65 nm CMOS technology, and its functionality is verified across process, voltage and tempe...

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Veröffentlicht in:Circuits, systems, and signal processing systems, and signal processing, 2020-08, Vol.39 (8), p.3819-3832
Hauptverfasser: Lad Kirankumar, H., Rekha, S., Laxminidhi, Tonse
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Rekha, S.
Laxminidhi, Tonse
description This paper presents a novel architecture for phase frequency detector (PFD) which eliminates the blind zone effect as well as the dead zone for a charge-pump phase-locked loop (CP-PLL). This PFD is designed in 65 nm CMOS technology, and its functionality is verified across process, voltage and temperature variations. Achieved maximum frequency of operation ( F max ) is 3.44 GHz which is suitable for high reference clocked fast settling PLLs. Proposed PFD consumes 324  μ W power from 1.2 V supply at maximum operating frequency. The area occupied by proposed circuit layout is 322.612  μ m 2 .
doi_str_mv 10.1007/s00034-020-01366-1
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subjects Charge pumps
Circuits
Circuits and Systems
CMOS
Electrical Engineering
Electronics and Microelectronics
Engineering
Instrumentation
Phase locked loops
Phase locked systems
Power consumption
Signal,Image and Speech Processing
title A Dead-Zone-Free Zero Blind-Zone High-Speed Phase Frequency Detector for Charge-Pump PLL
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