A Streaming Dataflow Engine for Sparse Matrix-Vector Multiplication Using High-Level Synthesis

Using high-level synthesis techniques, this paper proposes an adaptable high-performance streaming dataflow engine for sparse matrix dense vector multiplication (SpMV) suitable for embedded FPGAs. As the SpMV is a memory-bound algorithm, this engine combines the three concepts of loop pipelining , d...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems 2020-06, Vol.39 (6), p.1272-1285
Hauptverfasser:	Hosseinabady, Mohammad, Nunez-Yanez, Jose Luis
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithms Computer architecture Data transmission Edge computing energy Energy consumption Engines Field programmable gate arrays FPGA Hardware High level synthesis high-level synthesis (HLS) Machine learning Mathematical analysis Matrix algebra Matrix methods Multiplication Optimization Pipelining (computers) Sparse matrices sparse-matrix-vector Sparsity support vector machine (SVM) Support vector machines
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