Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run
A novel test pattern generation method for multiple dc and ac faults is presented. The fault models considered include line stuck-at, bridging, transition, and transistor stuck-open faults. All faults are transformed into stuck-at faults with some constraints in the proposed two-timeframe circuit mo...
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| Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 2020-06, Vol.39 (6), p.1340-1345 |
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| container_title | IEEE transactions on computer-aided design of integrated circuits and systems |
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| creator | Kung, Yi-Cheng Lee, Kuen-Jong Reddy, Sudhakar M. |
| description | A novel test pattern generation method for multiple dc and ac faults is presented. The fault models considered include line stuck-at, bridging, transition, and transistor stuck-open faults. All faults are transformed into stuck-at faults with some constraints in the proposed two-timeframe circuit model such that all considered faults can be represented utilizing the user-defined fault model supported currently by most commercial ATPG tools. This makes it possible to generate a compact set of patterns for both dc and ac faults in one ATPG run without needing to modify the ATPG tool. Both launch-on-capture and launch-on-shift test methods are supported. The experimental results on ISCAS'89 and ITC'99 benchmark circuits show the effectiveness of the proposed method (PM) compared to earlier PMs. |
| doi_str_mv | 10.1109/TCAD.2019.2921345 |
| format | Article |
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The fault models considered include line stuck-at, bridging, transition, and transistor stuck-open faults. All faults are transformed into stuck-at faults with some constraints in the proposed two-timeframe circuit model such that all considered faults can be represented utilizing the user-defined fault model supported currently by most commercial ATPG tools. This makes it possible to generate a compact set of patterns for both dc and ac faults in one ATPG run without needing to modify the ATPG tool. Both launch-on-capture and launch-on-shift test methods are supported. The experimental results on ISCAS'89 and ITC'99 benchmark circuits show the effectiveness of the proposed method (PM) compared to earlier PMs.</description><identifier>ISSN: 0278-0070</identifier><identifier>EISSN: 1937-4151</identifier><identifier>DOI: 10.1109/TCAD.2019.2921345</identifier><identifier>CODEN: ITCSDI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>AC faults ; ATPG ; Circuit faults ; Circuits ; CMOS ; Constraint modelling ; DC faults ; Fault location ; Integrated circuit modeling ; Logic gates ; Pattern generation ; Stuck open faults ; test compaction ; Test pattern generators ; Transistors</subject><ispartof>IEEE transactions on computer-aided design of integrated circuits and systems, 2020-06, Vol.39 (6), p.1340-1345</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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The fault models considered include line stuck-at, bridging, transition, and transistor stuck-open faults. All faults are transformed into stuck-at faults with some constraints in the proposed two-timeframe circuit model such that all considered faults can be represented utilizing the user-defined fault model supported currently by most commercial ATPG tools. This makes it possible to generate a compact set of patterns for both dc and ac faults in one ATPG run without needing to modify the ATPG tool. Both launch-on-capture and launch-on-shift test methods are supported. The experimental results on ISCAS'89 and ITC'99 benchmark circuits show the effectiveness of the proposed method (PM) compared to earlier PMs.</description><subject>AC faults</subject><subject>ATPG</subject><subject>Circuit faults</subject><subject>Circuits</subject><subject>CMOS</subject><subject>Constraint modelling</subject><subject>DC faults</subject><subject>Fault location</subject><subject>Integrated circuit modeling</subject><subject>Logic gates</subject><subject>Pattern generation</subject><subject>Stuck open faults</subject><subject>test compaction</subject><subject>Test pattern generators</subject><subject>Transistors</subject><issn>0278-0070</issn><issn>1937-4151</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kMlOwzAURS0EEmX4AMTGEusUT0mcZZXSgtSqFQ0bNpZjv6BUwSl2suDvcdWKzRuke99wEHqgZEopKZ6rcjafMkKLKSsY5SK9QBNa8DwRNKWXaEJYLhNCcnKNbkLYE0JFyooJ-lyCA6-H1n3hXQwdJFg7i-f9WMd6q4cBvMMVhCHgpvd4PXZDe-gAl-vNDi90bPG6t9AF3Dq8cYBn1XaJ30d3h64a3QW4P-db9LF4qcrXZLVZvpWzVWJYwYdEpkY2dWZqajNrQRtraGNFU2tuUsaMZLXWREtBpBXxMxDE5FRaxrSUmZD8Fj2d5h58_zPGQ9W-H72LKxUTJMsJY1kaVfSkMr4PwUOjDr791v5XUaKOCNURoToiVGeE0fN48rQA8K-XOWc8Lfgfej1rog</recordid><startdate>20200601</startdate><enddate>20200601</enddate><creator>Kung, Yi-Cheng</creator><creator>Lee, Kuen-Jong</creator><creator>Reddy, Sudhakar M.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | AC faults ATPG Circuit faults Circuits CMOS Constraint modelling DC faults Fault location Integrated circuit modeling Logic gates Pattern generation Stuck open faults test compaction Test pattern generators Transistors |
| title | Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run |
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