Dual-Mode FPGA-Based Triple-TDC With Real-Time Calibration and a Triple Modular Redundancy Scheme

This paper proposes a triple time-to-digital converter (TDC) for a field-programmable gate array (FPGA) platform with dual operation modes. First, the proposed triple-TDC employs the real-time calibration circuit followed by the traditional tapped delay line architecture to improve the environmental...

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Veröffentlicht in:	Electronics (Basel) 2020-04, Vol.9 (4), p.607
1. Verfasser:	Chen, Yuan-Ho
Format:	Artikel
Sprache:	eng
Schlagworte:	Calibration Circuits Converters Delay lines Design Environmental effects Field programmable gate arrays Linearity Nonlinearity Real time Redundancy Researchers Single mode operation
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