Transformation and dynamic visualization of images from computer through an FPGA in a matrix of LED

Around the transformations [11], extraction of characteristics [12] or any other type of massive matrix operation, object detection and recognition and route planning, Programmable Logic Devices (PLD) have been used, since they require low power and a small amount of space to work [13, 14] in additi...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:Telkomnika 2019-12, Vol.17 (6), p.3003-3009
Hauptverfasser: Gómez, Edwar Jacinto, Santa, Fernando Martínez, Ariza, Holman Montiel
Format: Artikel
Sprache:eng
Schlagworte:
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 3009
container_issue 6
container_start_page 3003
container_title Telkomnika
container_volume 17
creator Gómez, Edwar Jacinto
Santa, Fernando Martínez
Ariza, Holman Montiel
description Around the transformations [11], extraction of characteristics [12] or any other type of massive matrix operation, object detection and recognition and route planning, Programmable Logic Devices (PLD) have been used, since they require low power and a small amount of space to work [13, 14] in addition to having the ability to perform real-time implementations, working with static and moving images [15], which requires thousands of iterations per second, with maximum use of FPGA resources, both in the combinatorial part (LUT) as in its storage part (memory bank), making efficient the implementations made with this type of devices [16, 17]. The flexibility and performance of hardware development using standard hardware description languages, regardless of the size and architectures of different FPGA's, offers the possibility to test and compare different algorithm resolution methods, which could give different solutions and indicate what family and what architecture would be the most appropriate to use in digital image processing applications [22, 23], using the combination of Soft Cores together with hardware designed to accelerate information processing. The work done begins with the design of a software script on the personal computer, which sends the data of the digital image in binary-ascii format through a serial port emulated towards the FPGA, after that, the programmable logic device processes the information, sends the data to a power system that supports the electrical requirements at the speed required by the array of LEDs and in this way the correct visualization of the information is made. 3.Implementation and Results The first part of the work is shown in the following code, the script reads different formats of images (jpg, png and gif), it will make the conversion to a matrix of valor to create the ROM file, it will be read for the FPGA and put in to LED matrix. imread () /imshow () to verify that it is in full form for processing. im = imread('Mario_8bits.PNG'); figure () imshow(im) In the following code segment, to scale the image the imresize () function is used, which gives us the facility of scaling the value of a square or rectangular matrix to the size to be visualized in the array of LEDs, a bicubic interpolation algorithm was used, a process that guarantees that do not drastically change the information that will be sent to the FPGA. im_small = imresize(im, [32 32], 'cubic'); figure () imshow(im_small) The next code shown that the ma
doi_str_mv 10.12928/telkomnika.v17i6.12710
format Article
fullrecord <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_journals_2386936605</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>2386936605</sourcerecordid><originalsourceid>FETCH-LOGICAL-c1950-77654d7c292214f701a3c25290d41906c451916203d15847acd94b61521ec5913</originalsourceid><addsrcrecordid>eNpFUNFKAzEQDKJgqf0GAz5fzSaX5PJYaluFgj7U5xBzd23a3qUmd8X69cZWcGFZ2J2ZZQaheyBjoIoWj1213_mmdTszPoJ0Iq0lkCs0oIzQTFHFrtEAhGJZanKLRjFuSSpJKFfFANlVMG2sfWhM53yLTVvi8tSaxll8dLE3e_d9ufgau8asq4jr4BtsfXPouyrgbhN8v94kJp6_LSbYJRGc1IL7-uUsZ0936KY2-1iN_uYQvc9nq-lztnxdvEwny8yC4iSTUvC8lDb5opDXkoBhlnKqSJmDIsLmHBQISlgJvMilsaXKPwRwCpXlCtgQPVx0D8F_9lXs9Nb3oU0vNWVF8i8E4QklLygbfIyhqvUhJGPhpIHoc6j6P1R9DlWfQ2U_Bjdsmg</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2386936605</pqid></control><display><type>article</type><title>Transformation and dynamic visualization of images from computer through an FPGA in a matrix of LED</title><source>EZB-FREE-00999 freely available EZB journals</source><creator>Gómez, Edwar Jacinto ; Santa, Fernando Martínez ; Ariza, Holman Montiel</creator><creatorcontrib>Gómez, Edwar Jacinto ; Santa, Fernando Martínez ; Ariza, Holman Montiel</creatorcontrib><description>Around the transformations [11], extraction of characteristics [12] or any other type of massive matrix operation, object detection and recognition and route planning, Programmable Logic Devices (PLD) have been used, since they require low power and a small amount of space to work [13, 14] in addition to having the ability to perform real-time implementations, working with static and moving images [15], which requires thousands of iterations per second, with maximum use of FPGA resources, both in the combinatorial part (LUT) as in its storage part (memory bank), making efficient the implementations made with this type of devices [16, 17]. The flexibility and performance of hardware development using standard hardware description languages, regardless of the size and architectures of different FPGA's, offers the possibility to test and compare different algorithm resolution methods, which could give different solutions and indicate what family and what architecture would be the most appropriate to use in digital image processing applications [22, 23], using the combination of Soft Cores together with hardware designed to accelerate information processing. The work done begins with the design of a software script on the personal computer, which sends the data of the digital image in binary-ascii format through a serial port emulated towards the FPGA, after that, the programmable logic device processes the information, sends the data to a power system that supports the electrical requirements at the speed required by the array of LEDs and in this way the correct visualization of the information is made. 3.Implementation and Results The first part of the work is shown in the following code, the script reads different formats of images (jpg, png and gif), it will make the conversion to a matrix of valor to create the ROM file, it will be read for the FPGA and put in to LED matrix. imread () /imshow () to verify that it is in full form for processing. im = imread('Mario_8bits.PNG'); figure () imshow(im) In the following code segment, to scale the image the imresize () function is used, which gives us the facility of scaling the value of a square or rectangular matrix to the size to be visualized in the array of LEDs, a bicubic interpolation algorithm was used, a process that guarantees that do not drastically change the information that will be sent to the FPGA. im_small = imresize(im, [32 32], 'cubic'); figure () imshow(im_small) The next code shown that the matrices for the images that are entered were defined for a size of 32x32 being this a square matrix, the selection of the size is based on the space to occupy within the ROM memories that will be of 1024 bits maximum size of each block of memory of a standard FPGA, which has a capacity of 8 times the value of each block generated. im_small_r = im_small(:, im_small_g = im_small(:, im small b = im small(:, The image already scaled is broken down into the 3 matrices of the channels that make up a digital image R (network), G (green) and B (blue), maintaining the intensity characteristics to conform the different color possibilities, in each matrix the values of each pixel have a magnitude between 0 and 255. The input channel of the module (seriai_in) receives the data to work with the waiting of a rising edge for the transmission of the 8 bits. (data_out) is the parallel output of the received data. (read_buffer) in high state of responsible for the transmission of the data to a FIFO memory. (reset_buffer) in active state delete the data saved under the count of 16 data blocks. (en_i6_x_baud) in active state makes the counting of 16 cycles of 8 bits which culminates the storage so that the entire block created in the 16x8 memory will be transmitted. (buffer_data_present) gives an input prompt or that there is information block in the memory. (buffer_fuii or buffer_haif_fuii) indicates in high mode the full state of the memory, indicates how their names say full or half full 16x8/8x8 when it is full memory communicates this state and activates the complete transfer of the memory block wherever your processing is necessary. (cik) system clock for a synchronous multiple system. 3.2.Reception and Storage of Blocks of Information in RAM In the design and implementation of the system it is observed how the CORE of the Uart provided by Xilinx is controlled, by means of a finite state machine, this is in charge of reading the data from the FIFO memory and passing it to the internal RAM memory of the FPGA, in this way it is possible to read blocks of information from the USB-Serial port of the computer to the internal memory, which will then be responsible for displaying the information, as shown in Figure 4.</description><identifier>ISSN: 1693-6930</identifier><identifier>EISSN: 2302-9293</identifier><identifier>DOI: 10.12928/telkomnika.v17i6.12710</identifier><language>eng</language><publisher>Yogyakarta: Ahmad Dahlan University</publisher><subject>Algorithms ; Buffers ; Combinatorial analysis ; Counting ; Data buses ; Data processing ; Design ; Digital computers ; Digital imaging ; Electric power systems ; Field programmable gate arrays ; Finite state machines ; Hardware description languages ; Image processing ; Information processing ; Interpolation ; Light emitting diodes ; Moving images ; Object recognition ; Personal computers ; Power management ; Programmable logic devices ; Random access memory ; Route planning ; Transformations (mathematics) ; Visualization</subject><ispartof>Telkomnika, 2019-12, Vol.17 (6), p.3003-3009</ispartof><rights>2019. This work is published under https://creativecommons.org/licenses/by/3.0 (the “License”). Notwithstanding the ProQuest Terms and Conditions, you may use this content in accordance with the terms of the License.</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,780,784,27924,27925</link.rule.ids></links><search><creatorcontrib>Gómez, Edwar Jacinto</creatorcontrib><creatorcontrib>Santa, Fernando Martínez</creatorcontrib><creatorcontrib>Ariza, Holman Montiel</creatorcontrib><title>Transformation and dynamic visualization of images from computer through an FPGA in a matrix of LED</title><title>Telkomnika</title><description>Around the transformations [11], extraction of characteristics [12] or any other type of massive matrix operation, object detection and recognition and route planning, Programmable Logic Devices (PLD) have been used, since they require low power and a small amount of space to work [13, 14] in addition to having the ability to perform real-time implementations, working with static and moving images [15], which requires thousands of iterations per second, with maximum use of FPGA resources, both in the combinatorial part (LUT) as in its storage part (memory bank), making efficient the implementations made with this type of devices [16, 17]. The flexibility and performance of hardware development using standard hardware description languages, regardless of the size and architectures of different FPGA's, offers the possibility to test and compare different algorithm resolution methods, which could give different solutions and indicate what family and what architecture would be the most appropriate to use in digital image processing applications [22, 23], using the combination of Soft Cores together with hardware designed to accelerate information processing. The work done begins with the design of a software script on the personal computer, which sends the data of the digital image in binary-ascii format through a serial port emulated towards the FPGA, after that, the programmable logic device processes the information, sends the data to a power system that supports the electrical requirements at the speed required by the array of LEDs and in this way the correct visualization of the information is made. 3.Implementation and Results The first part of the work is shown in the following code, the script reads different formats of images (jpg, png and gif), it will make the conversion to a matrix of valor to create the ROM file, it will be read for the FPGA and put in to LED matrix. imread () /imshow () to verify that it is in full form for processing. im = imread('Mario_8bits.PNG'); figure () imshow(im) In the following code segment, to scale the image the imresize () function is used, which gives us the facility of scaling the value of a square or rectangular matrix to the size to be visualized in the array of LEDs, a bicubic interpolation algorithm was used, a process that guarantees that do not drastically change the information that will be sent to the FPGA. im_small = imresize(im, [32 32], 'cubic'); figure () imshow(im_small) The next code shown that the matrices for the images that are entered were defined for a size of 32x32 being this a square matrix, the selection of the size is based on the space to occupy within the ROM memories that will be of 1024 bits maximum size of each block of memory of a standard FPGA, which has a capacity of 8 times the value of each block generated. im_small_r = im_small(:, im_small_g = im_small(:, im small b = im small(:, The image already scaled is broken down into the 3 matrices of the channels that make up a digital image R (network), G (green) and B (blue), maintaining the intensity characteristics to conform the different color possibilities, in each matrix the values of each pixel have a magnitude between 0 and 255. The input channel of the module (seriai_in) receives the data to work with the waiting of a rising edge for the transmission of the 8 bits. (data_out) is the parallel output of the received data. (read_buffer) in high state of responsible for the transmission of the data to a FIFO memory. (reset_buffer) in active state delete the data saved under the count of 16 data blocks. (en_i6_x_baud) in active state makes the counting of 16 cycles of 8 bits which culminates the storage so that the entire block created in the 16x8 memory will be transmitted. (buffer_data_present) gives an input prompt or that there is information block in the memory. (buffer_fuii or buffer_haif_fuii) indicates in high mode the full state of the memory, indicates how their names say full or half full 16x8/8x8 when it is full memory communicates this state and activates the complete transfer of the memory block wherever your processing is necessary. (cik) system clock for a synchronous multiple system. 3.2.Reception and Storage of Blocks of Information in RAM In the design and implementation of the system it is observed how the CORE of the Uart provided by Xilinx is controlled, by means of a finite state machine, this is in charge of reading the data from the FIFO memory and passing it to the internal RAM memory of the FPGA, in this way it is possible to read blocks of information from the USB-Serial port of the computer to the internal memory, which will then be responsible for displaying the information, as shown in Figure 4.</description><subject>Algorithms</subject><subject>Buffers</subject><subject>Combinatorial analysis</subject><subject>Counting</subject><subject>Data buses</subject><subject>Data processing</subject><subject>Design</subject><subject>Digital computers</subject><subject>Digital imaging</subject><subject>Electric power systems</subject><subject>Field programmable gate arrays</subject><subject>Finite state machines</subject><subject>Hardware description languages</subject><subject>Image processing</subject><subject>Information processing</subject><subject>Interpolation</subject><subject>Light emitting diodes</subject><subject>Moving images</subject><subject>Object recognition</subject><subject>Personal computers</subject><subject>Power management</subject><subject>Programmable logic devices</subject><subject>Random access memory</subject><subject>Route planning</subject><subject>Transformations (mathematics)</subject><subject>Visualization</subject><issn>1693-6930</issn><issn>2302-9293</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2019</creationdate><recordtype>article</recordtype><sourceid>ABUWG</sourceid><sourceid>AFKRA</sourceid><sourceid>AZQEC</sourceid><sourceid>BENPR</sourceid><sourceid>CCPQU</sourceid><sourceid>DWQXO</sourceid><recordid>eNpFUNFKAzEQDKJgqf0GAz5fzSaX5PJYaluFgj7U5xBzd23a3qUmd8X69cZWcGFZ2J2ZZQaheyBjoIoWj1213_mmdTszPoJ0Iq0lkCs0oIzQTFHFrtEAhGJZanKLRjFuSSpJKFfFANlVMG2sfWhM53yLTVvi8tSaxll8dLE3e_d9ufgau8asq4jr4BtsfXPouyrgbhN8v94kJp6_LSbYJRGc1IL7-uUsZ0936KY2-1iN_uYQvc9nq-lztnxdvEwny8yC4iSTUvC8lDb5opDXkoBhlnKqSJmDIsLmHBQISlgJvMilsaXKPwRwCpXlCtgQPVx0D8F_9lXs9Nb3oU0vNWVF8i8E4QklLygbfIyhqvUhJGPhpIHoc6j6P1R9DlWfQ2U_Bjdsmg</recordid><startdate>20191201</startdate><enddate>20191201</enddate><creator>Gómez, Edwar Jacinto</creator><creator>Santa, Fernando Martínez</creator><creator>Ariza, Holman Montiel</creator><general>Ahmad Dahlan University</general><scope>AAYXX</scope><scope>CITATION</scope><scope>8FE</scope><scope>8FG</scope><scope>ABUWG</scope><scope>AFKRA</scope><scope>ARAPS</scope><scope>AZQEC</scope><scope>BENPR</scope><scope>BGLVJ</scope><scope>BVBZV</scope><scope>CCPQU</scope><scope>DWQXO</scope><scope>HCIFZ</scope><scope>P5Z</scope><scope>P62</scope><scope>PIMPY</scope><scope>PQEST</scope><scope>PQQKQ</scope><scope>PQUKI</scope><scope>PRINS</scope></search><sort><creationdate>20191201</creationdate><title>Transformation and dynamic visualization of images from computer through an FPGA in a matrix of LED</title><author>Gómez, Edwar Jacinto ; Santa, Fernando Martínez ; Ariza, Holman Montiel</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c1950-77654d7c292214f701a3c25290d41906c451916203d15847acd94b61521ec5913</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2019</creationdate><topic>Algorithms</topic><topic>Buffers</topic><topic>Combinatorial analysis</topic><topic>Counting</topic><topic>Data buses</topic><topic>Data processing</topic><topic>Design</topic><topic>Digital computers</topic><topic>Digital imaging</topic><topic>Electric power systems</topic><topic>Field programmable gate arrays</topic><topic>Finite state machines</topic><topic>Hardware description languages</topic><topic>Image processing</topic><topic>Information processing</topic><topic>Interpolation</topic><topic>Light emitting diodes</topic><topic>Moving images</topic><topic>Object recognition</topic><topic>Personal computers</topic><topic>Power management</topic><topic>Programmable logic devices</topic><topic>Random access memory</topic><topic>Route planning</topic><topic>Transformations (mathematics)</topic><topic>Visualization</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Gómez, Edwar Jacinto</creatorcontrib><creatorcontrib>Santa, Fernando Martínez</creatorcontrib><creatorcontrib>Ariza, Holman Montiel</creatorcontrib><collection>CrossRef</collection><collection>ProQuest SciTech Collection</collection><collection>ProQuest Technology Collection</collection><collection>ProQuest Central (Alumni Edition)</collection><collection>ProQuest Central UK/Ireland</collection><collection>Advanced Technologies &amp; Aerospace Collection</collection><collection>ProQuest Central Essentials</collection><collection>ProQuest Central</collection><collection>Technology Collection</collection><collection>East &amp; South Asia Database</collection><collection>ProQuest One Community College</collection><collection>ProQuest Central Korea</collection><collection>SciTech Premium Collection</collection><collection>Advanced Technologies &amp; Aerospace Database</collection><collection>ProQuest Advanced Technologies &amp; Aerospace Collection</collection><collection>Access via ProQuest (Open Access)</collection><collection>ProQuest One Academic Eastern Edition (DO NOT USE)</collection><collection>ProQuest One Academic</collection><collection>ProQuest One Academic UKI Edition</collection><collection>ProQuest Central China</collection><jtitle>Telkomnika</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Gómez, Edwar Jacinto</au><au>Santa, Fernando Martínez</au><au>Ariza, Holman Montiel</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Transformation and dynamic visualization of images from computer through an FPGA in a matrix of LED</atitle><jtitle>Telkomnika</jtitle><date>2019-12-01</date><risdate>2019</risdate><volume>17</volume><issue>6</issue><spage>3003</spage><epage>3009</epage><pages>3003-3009</pages><issn>1693-6930</issn><eissn>2302-9293</eissn><abstract>Around the transformations [11], extraction of characteristics [12] or any other type of massive matrix operation, object detection and recognition and route planning, Programmable Logic Devices (PLD) have been used, since they require low power and a small amount of space to work [13, 14] in addition to having the ability to perform real-time implementations, working with static and moving images [15], which requires thousands of iterations per second, with maximum use of FPGA resources, both in the combinatorial part (LUT) as in its storage part (memory bank), making efficient the implementations made with this type of devices [16, 17]. The flexibility and performance of hardware development using standard hardware description languages, regardless of the size and architectures of different FPGA's, offers the possibility to test and compare different algorithm resolution methods, which could give different solutions and indicate what family and what architecture would be the most appropriate to use in digital image processing applications [22, 23], using the combination of Soft Cores together with hardware designed to accelerate information processing. The work done begins with the design of a software script on the personal computer, which sends the data of the digital image in binary-ascii format through a serial port emulated towards the FPGA, after that, the programmable logic device processes the information, sends the data to a power system that supports the electrical requirements at the speed required by the array of LEDs and in this way the correct visualization of the information is made. 3.Implementation and Results The first part of the work is shown in the following code, the script reads different formats of images (jpg, png and gif), it will make the conversion to a matrix of valor to create the ROM file, it will be read for the FPGA and put in to LED matrix. imread () /imshow () to verify that it is in full form for processing. im = imread('Mario_8bits.PNG'); figure () imshow(im) In the following code segment, to scale the image the imresize () function is used, which gives us the facility of scaling the value of a square or rectangular matrix to the size to be visualized in the array of LEDs, a bicubic interpolation algorithm was used, a process that guarantees that do not drastically change the information that will be sent to the FPGA. im_small = imresize(im, [32 32], 'cubic'); figure () imshow(im_small) The next code shown that the matrices for the images that are entered were defined for a size of 32x32 being this a square matrix, the selection of the size is based on the space to occupy within the ROM memories that will be of 1024 bits maximum size of each block of memory of a standard FPGA, which has a capacity of 8 times the value of each block generated. im_small_r = im_small(:, im_small_g = im_small(:, im small b = im small(:, The image already scaled is broken down into the 3 matrices of the channels that make up a digital image R (network), G (green) and B (blue), maintaining the intensity characteristics to conform the different color possibilities, in each matrix the values of each pixel have a magnitude between 0 and 255. The input channel of the module (seriai_in) receives the data to work with the waiting of a rising edge for the transmission of the 8 bits. (data_out) is the parallel output of the received data. (read_buffer) in high state of responsible for the transmission of the data to a FIFO memory. (reset_buffer) in active state delete the data saved under the count of 16 data blocks. (en_i6_x_baud) in active state makes the counting of 16 cycles of 8 bits which culminates the storage so that the entire block created in the 16x8 memory will be transmitted. (buffer_data_present) gives an input prompt or that there is information block in the memory. (buffer_fuii or buffer_haif_fuii) indicates in high mode the full state of the memory, indicates how their names say full or half full 16x8/8x8 when it is full memory communicates this state and activates the complete transfer of the memory block wherever your processing is necessary. (cik) system clock for a synchronous multiple system. 3.2.Reception and Storage of Blocks of Information in RAM In the design and implementation of the system it is observed how the CORE of the Uart provided by Xilinx is controlled, by means of a finite state machine, this is in charge of reading the data from the FIFO memory and passing it to the internal RAM memory of the FPGA, in this way it is possible to read blocks of information from the USB-Serial port of the computer to the internal memory, which will then be responsible for displaying the information, as shown in Figure 4.</abstract><cop>Yogyakarta</cop><pub>Ahmad Dahlan University</pub><doi>10.12928/telkomnika.v17i6.12710</doi><tpages>7</tpages><oa>free_for_read</oa></addata></record>
fulltext fulltext
identifier ISSN: 1693-6930
ispartof Telkomnika, 2019-12, Vol.17 (6), p.3003-3009
issn 1693-6930
2302-9293
language eng
recordid cdi_proquest_journals_2386936605
source EZB-FREE-00999 freely available EZB journals
subjects Algorithms
Buffers
Combinatorial analysis
Counting
Data buses
Data processing
Design
Digital computers
Digital imaging
Electric power systems
Field programmable gate arrays
Finite state machines
Hardware description languages
Image processing
Information processing
Interpolation
Light emitting diodes
Moving images
Object recognition
Personal computers
Power management
Programmable logic devices
Random access memory
Route planning
Transformations (mathematics)
Visualization
title Transformation and dynamic visualization of images from computer through an FPGA in a matrix of LED
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-24T00%3A56%3A56IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Transformation%20and%20dynamic%20visualization%20of%20images%20from%20computer%20through%20an%20FPGA%20in%20a%20matrix%20of%20LED&rft.jtitle=Telkomnika&rft.au=G%C3%B3mez,%20Edwar%20Jacinto&rft.date=2019-12-01&rft.volume=17&rft.issue=6&rft.spage=3003&rft.epage=3009&rft.pages=3003-3009&rft.issn=1693-6930&rft.eissn=2302-9293&rft_id=info:doi/10.12928/telkomnika.v17i6.12710&rft_dat=%3Cproquest_cross%3E2386936605%3C/proquest_cross%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2386936605&rft_id=info:pmid/&rfr_iscdi=true