Time efficient systolic architecture for matrix vector multiplication

A modified systolic array architecture for performing matrix vector operation is presented. The vector to be transformed is represented at bit level as a matrix having only binary elements which are multiplied with a weight vector whose i th element is 2 i−1. This modification permits pipelining of...

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Veröffentlicht in:Information processing letters 1987-03, Vol.24 (4), p.225-231
Hauptverfasser: Zubair, M., Madan, B.B.
Format: Artikel
Sprache:eng
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