Time efficient systolic architecture for matrix vector multiplication
A modified systolic array architecture for performing matrix vector operation is presented. The vector to be transformed is represented at bit level as a matrix having only binary elements which are multiplied with a weight vector whose i th element is 2 i−1. This modification permits pipelining of...
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| Veröffentlicht in: | Information processing letters 1987-03, Vol.24 (4), p.225-231 |
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| creator | Zubair, M. Madan, B.B. |
| description | A modified systolic array architecture for performing matrix vector operation is presented. The vector to be transformed is represented at bit level as a matrix having only binary elements which are multiplied with a weight vector whose i
th element is 2
i−1. This modification permits pipelining of verious carry-save adder stages of the multiplier and thereby permitting increased data throughput. It is shown that the throughput rate of the proposed design is independent of the vector size and the word length in contrast to the previously reported architecture by Kung and Liserson (1978). Detailed area time complexity analysis of the proposed design has also been carried out. |
| doi_str_mv | 10.1016/0020-0190(87)90138-4 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_journals_237277480</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><els_id>0020019087901384</els_id><sourcerecordid>1136780</sourcerecordid><originalsourceid>FETCH-LOGICAL-c224t-8dc1c3bf324ed8a86d8b5b39a53a6e808a482d8254097a17d858af81499999c13</originalsourceid><addsrcrecordid>eNp9kEtLAzEQgIMoWKv_wMMiHvSwmtduZi-ClPqAgpd6Dmk2wZTtbk2yxf57s27p0bkMM3wzw3wIXRP8QDApHzGmOMekwncg7itMGOT8BE0ICJqXhFSnaHJEztFFCGuMccmZmKD50m1MZqx12pk2ZmEfYtc4nSmvv1w0OvbeZLbz2UZF736yXWoNVd9Et02giq5rL9GZVU0wV4c8RZ8v8-XsLV98vL7Pnhe5ppTHHGpNNFtZRrmpQUFZw6pYsUoVTJUGMCgOtAZacFwJRUQNBSgLhFdDaMKm6Gbcu_Xdd29ClOuu9206KSkTVAgOOEF8hLTvQvDGyq13G-X3kmA5-JKDDDnIkCDkny_J09jtYbcKWjXWq1a7cJwFClxAmbCnETPpz50zXobBnDa180mNrDv3_51fD3t9_A</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>237277480</pqid></control><display><type>article</type><title>Time efficient systolic architecture for matrix vector multiplication</title><source>Elsevier ScienceDirect Journals</source><creator>Zubair, M. ; Madan, B.B.</creator><creatorcontrib>Zubair, M. ; Madan, B.B.</creatorcontrib><description>A modified systolic array architecture for performing matrix vector operation is presented. The vector to be transformed is represented at bit level as a matrix having only binary elements which are multiplied with a weight vector whose i
th element is 2
i−1. This modification permits pipelining of verious carry-save adder stages of the multiplier and thereby permitting increased data throughput. It is shown that the throughput rate of the proposed design is independent of the vector size and the word length in contrast to the previously reported architecture by Kung and Liserson (1978). Detailed area time complexity analysis of the proposed design has also been carried out.</description><identifier>ISSN: 0020-0190</identifier><identifier>EISSN: 1872-6119</identifier><identifier>DOI: 10.1016/0020-0190(87)90138-4</identifier><identifier>CODEN: IFPLAT</identifier><language>eng</language><publisher>Amsterdam: Elsevier B.V</publisher><subject>Algorithmics. Computability. Computer arithmetics ; Applied sciences ; Architecture ; Computer science ; Computer science; control theory; systems ; Exact sciences and technology ; Mathematical analysis ; Matrix ; Systems design ; Theoretical computing ; VLSI</subject><ispartof>Information processing letters, 1987-03, Vol.24 (4), p.225-231</ispartof><rights>1987</rights><rights>1987 INIST-CNRS</rights><rights>Copyright Elsevier Sequoia S.A. Mar 2, 1987</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c224t-8dc1c3bf324ed8a86d8b5b39a53a6e808a482d8254097a17d858af81499999c13</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://dx.doi.org/10.1016/0020-0190(87)90138-4$$EHTML$$P50$$Gelsevier$$H</linktohtml><link.rule.ids>314,777,781,3537,27905,27906,45976</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=8284786$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Zubair, M.</creatorcontrib><creatorcontrib>Madan, B.B.</creatorcontrib><title>Time efficient systolic architecture for matrix vector multiplication</title><title>Information processing letters</title><description>A modified systolic array architecture for performing matrix vector operation is presented. The vector to be transformed is represented at bit level as a matrix having only binary elements which are multiplied with a weight vector whose i
th element is 2
i−1. This modification permits pipelining of verious carry-save adder stages of the multiplier and thereby permitting increased data throughput. It is shown that the throughput rate of the proposed design is independent of the vector size and the word length in contrast to the previously reported architecture by Kung and Liserson (1978). Detailed area time complexity analysis of the proposed design has also been carried out.</description><subject>Algorithmics. Computability. Computer arithmetics</subject><subject>Applied sciences</subject><subject>Architecture</subject><subject>Computer science</subject><subject>Computer science; control theory; systems</subject><subject>Exact sciences and technology</subject><subject>Mathematical analysis</subject><subject>Matrix</subject><subject>Systems design</subject><subject>Theoretical computing</subject><subject>VLSI</subject><issn>0020-0190</issn><issn>1872-6119</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1987</creationdate><recordtype>article</recordtype><recordid>eNp9kEtLAzEQgIMoWKv_wMMiHvSwmtduZi-ClPqAgpd6Dmk2wZTtbk2yxf57s27p0bkMM3wzw3wIXRP8QDApHzGmOMekwncg7itMGOT8BE0ICJqXhFSnaHJEztFFCGuMccmZmKD50m1MZqx12pk2ZmEfYtc4nSmvv1w0OvbeZLbz2UZF736yXWoNVd9Et02giq5rL9GZVU0wV4c8RZ8v8-XsLV98vL7Pnhe5ppTHHGpNNFtZRrmpQUFZw6pYsUoVTJUGMCgOtAZacFwJRUQNBSgLhFdDaMKm6Gbcu_Xdd29ClOuu9206KSkTVAgOOEF8hLTvQvDGyq13G-X3kmA5-JKDDDnIkCDkny_J09jtYbcKWjXWq1a7cJwFClxAmbCnETPpz50zXobBnDa180mNrDv3_51fD3t9_A</recordid><startdate>19870302</startdate><enddate>19870302</enddate><creator>Zubair, M.</creator><creator>Madan, B.B.</creator><general>Elsevier B.V</general><general>Elsevier Science</general><general>Elsevier Sequoia S.A</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>19870302</creationdate><title>Time efficient systolic architecture for matrix vector multiplication</title><author>Zubair, M. ; Madan, B.B.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c224t-8dc1c3bf324ed8a86d8b5b39a53a6e808a482d8254097a17d858af81499999c13</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1987</creationdate><topic>Algorithmics. Computability. Computer arithmetics</topic><topic>Applied sciences</topic><topic>Architecture</topic><topic>Computer science</topic><topic>Computer science; control theory; systems</topic><topic>Exact sciences and technology</topic><topic>Mathematical analysis</topic><topic>Matrix</topic><topic>Systems design</topic><topic>Theoretical computing</topic><topic>VLSI</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Zubair, M.</creatorcontrib><creatorcontrib>Madan, B.B.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>Information processing letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Zubair, M.</au><au>Madan, B.B.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Time efficient systolic architecture for matrix vector multiplication</atitle><jtitle>Information processing letters</jtitle><date>1987-03-02</date><risdate>1987</risdate><volume>24</volume><issue>4</issue><spage>225</spage><epage>231</epage><pages>225-231</pages><issn>0020-0190</issn><eissn>1872-6119</eissn><coden>IFPLAT</coden><abstract>A modified systolic array architecture for performing matrix vector operation is presented. The vector to be transformed is represented at bit level as a matrix having only binary elements which are multiplied with a weight vector whose i
th element is 2
i−1. This modification permits pipelining of verious carry-save adder stages of the multiplier and thereby permitting increased data throughput. It is shown that the throughput rate of the proposed design is independent of the vector size and the word length in contrast to the previously reported architecture by Kung and Liserson (1978). Detailed area time complexity analysis of the proposed design has also been carried out.</abstract><cop>Amsterdam</cop><pub>Elsevier B.V</pub><doi>10.1016/0020-0190(87)90138-4</doi><tpages>7</tpages></addata></record> |
| fulltext | fulltext |
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| ispartof | Information processing letters, 1987-03, Vol.24 (4), p.225-231 |
| issn | 0020-0190 1872-6119 |
| language | eng |
| recordid | cdi_proquest_journals_237277480 |
| source | Elsevier ScienceDirect Journals |
| subjects | Algorithmics. Computability. Computer arithmetics Applied sciences Architecture Computer science Computer science control theory systems Exact sciences and technology Mathematical analysis Matrix Systems design Theoretical computing VLSI |
| title | Time efficient systolic architecture for matrix vector multiplication |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-18T04%3A39%3A03IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Time%20efficient%20systolic%20architecture%20for%20matrix%20vector%20multiplication&rft.jtitle=Information%20processing%20letters&rft.au=Zubair,%20M.&rft.date=1987-03-02&rft.volume=24&rft.issue=4&rft.spage=225&rft.epage=231&rft.pages=225-231&rft.issn=0020-0190&rft.eissn=1872-6119&rft.coden=IFPLAT&rft_id=info:doi/10.1016/0020-0190(87)90138-4&rft_dat=%3Cproquest_cross%3E1136780%3C/proquest_cross%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=237277480&rft_id=info:pmid/&rft_els_id=0020019087901384&rfr_iscdi=true |