A Novel Confined Nitride-Trapping Layer Device for 3-D NAND Flash With Robust Retention Performances

A novel confined nitride (SiN) charge trapping 3-D NAND flash with excellent postcycling retention performances was demonstrated. Using a uniform sidewall lateral recess in the 3-D stack followed by a SiN pull-back process to isolate the SiN trapping layer in a self-aligned way is critical to facili...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE transactions on electron devices 2020-03, Vol.67 (3), p.989-994
Hauptverfasser: Fu, Chung-Hao, Lue, Hang-Ting, Hsu, Tzu-Hsuan, Chen, Wei-Chen, Lee, Guan-Ru, Chiu, Chia-Jung, Wang, Keh-Chung, Lu, Chih-Yuan
Format: Artikel
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 994
container_issue 3
container_start_page 989
container_title IEEE transactions on electron devices
container_volume 67
creator Fu, Chung-Hao
Lue, Hang-Ting
Hsu, Tzu-Hsuan
Chen, Wei-Chen
Lee, Guan-Ru
Chiu, Chia-Jung
Wang, Keh-Chung
Lu, Chih-Yuan
description A novel confined nitride (SiN) charge trapping 3-D NAND flash with excellent postcycling retention performances was demonstrated. Using a uniform sidewall lateral recess in the 3-D stack followed by a SiN pull-back process to isolate the SiN trapping layer in a self-aligned way is critical to facilitate this structure. Lower erase saturation < −4 V was shown in the confined SiN cell because of discrete SiN along the {Z} -direction. Therefore, this structure is in favor of the larger memory window (>10 V) design. Random telegraph noise (RTN) characteristics are comparable to the traditional 3-D NAND device with < 0.1-V variation. Excellent single-level cell (SLC) retention with only ~600-mV charge loss after 125 °C one-week high-temperature baking for a post-1K-cycled device was obtained. It is far superior to the control sample without a confined SiN structure. Arrhenius analysis at various baking temperatures shows that the retention may pass>100 years at 60 °C and even longer at room temperature. Moreover, superior post-1K-cycled multilevel cell (MLC) retention was also illustrated, which even sustains 150 °C and one-week baking. Therefore, the device has the potential to meet the low-cost long-retention archive memory applications.
doi_str_mv 10.1109/TED.2020.2968805
format Article
fullrecord <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_journals_2368188030</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>8995774</ieee_id><sourcerecordid>2368188030</sourcerecordid><originalsourceid>FETCH-LOGICAL-c291t-a3c83cf13dd299fc4dd9691c88ea4db1ccd36945295458b66bcbfeae9e0c60223</originalsourceid><addsrcrecordid>eNo9kN9LwzAUhYMoOKfvgi8Bnzvzo82Sx7FuKowqY-JjSZNbl7E1NekG--_t2PDpcuA758KH0CMlI0qJelnN8hEjjIyYElKS7AoNaJaNEyVScY0GhFCZKC75LbqLcdNHkaZsgOwEF_4AWzz1Te0asLhwXXAWklXQbeuaH7zQRwg4h4MzgGsfME9yXEyKHM-3Oq7xt-vWeOmrfezwEjpoOucb_AmhZ3e6MRDv0U2ttxEeLneIvuaz1fQtWXy8vk8ni8QwRbtEcyO5qSm3lilVm9RaJRQ1UoJObUWNsVyoNGMqSzNZCVGZqgYNCogRhDE-RM_n3Tb43z3Ertz4fWj6lyXjQtLeCyc9Rc6UCT7GAHXZBrfT4VhSUp5clr3L8uSyvLjsK0_nigOAf1wqlY3HKf8DsTNvMg</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2368188030</pqid></control><display><type>article</type><title>A Novel Confined Nitride-Trapping Layer Device for 3-D NAND Flash With Robust Retention Performances</title><source>IEEE Electronic Library (IEL)</source><creator>Fu, Chung-Hao ; Lue, Hang-Ting ; Hsu, Tzu-Hsuan ; Chen, Wei-Chen ; Lee, Guan-Ru ; Chiu, Chia-Jung ; Wang, Keh-Chung ; Lu, Chih-Yuan</creator><creatorcontrib>Fu, Chung-Hao ; Lue, Hang-Ting ; Hsu, Tzu-Hsuan ; Chen, Wei-Chen ; Lee, Guan-Ru ; Chiu, Chia-Jung ; Wang, Keh-Chung ; Lu, Chih-Yuan</creatorcontrib><description><![CDATA[A novel confined nitride (SiN) charge trapping 3-D NAND flash with excellent postcycling retention performances was demonstrated. Using a uniform sidewall lateral recess in the 3-D stack followed by a SiN pull-back process to isolate the SiN trapping layer in a self-aligned way is critical to facilitate this structure. Lower erase saturation < −4 V was shown in the confined SiN cell because of discrete SiN along the <inline-formula> <tex-math notation="LaTeX">{Z} </tex-math></inline-formula>-direction. Therefore, this structure is in favor of the larger memory window (>10 V) design. Random telegraph noise (RTN) characteristics are comparable to the traditional 3-D NAND device with < 0.1-V variation. Excellent single-level cell (SLC) retention with only ~600-mV charge loss after 125 °C one-week high-temperature baking for a post-1K-cycled device was obtained. It is far superior to the control sample without a confined SiN structure. Arrhenius analysis at various baking temperatures shows that the retention may pass>100 years at 60 °C and even longer at room temperature. Moreover, superior post-1K-cycled multilevel cell (MLC) retention was also illustrated, which even sustains 150 °C and one-week baking. Therefore, the device has the potential to meet the low-cost long-retention archive memory applications.]]></description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2020.2968805</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>3-D nand ; archive memory ; Baking ; confined SiN ; long retention ; Nitrides ; Retention ; Room temperature ; Self alignment ; Trapping</subject><ispartof>IEEE transactions on electron devices, 2020-03, Vol.67 (3), p.989-994</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2020</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c291t-a3c83cf13dd299fc4dd9691c88ea4db1ccd36945295458b66bcbfeae9e0c60223</citedby><cites>FETCH-LOGICAL-c291t-a3c83cf13dd299fc4dd9691c88ea4db1ccd36945295458b66bcbfeae9e0c60223</cites><orcidid>0000-0002-3711-818X ; 0000-0001-9514-7686</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8995774$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27903,27904,54736</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8995774$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Fu, Chung-Hao</creatorcontrib><creatorcontrib>Lue, Hang-Ting</creatorcontrib><creatorcontrib>Hsu, Tzu-Hsuan</creatorcontrib><creatorcontrib>Chen, Wei-Chen</creatorcontrib><creatorcontrib>Lee, Guan-Ru</creatorcontrib><creatorcontrib>Chiu, Chia-Jung</creatorcontrib><creatorcontrib>Wang, Keh-Chung</creatorcontrib><creatorcontrib>Lu, Chih-Yuan</creatorcontrib><title>A Novel Confined Nitride-Trapping Layer Device for 3-D NAND Flash With Robust Retention Performances</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description><![CDATA[A novel confined nitride (SiN) charge trapping 3-D NAND flash with excellent postcycling retention performances was demonstrated. Using a uniform sidewall lateral recess in the 3-D stack followed by a SiN pull-back process to isolate the SiN trapping layer in a self-aligned way is critical to facilitate this structure. Lower erase saturation < −4 V was shown in the confined SiN cell because of discrete SiN along the <inline-formula> <tex-math notation="LaTeX">{Z} </tex-math></inline-formula>-direction. Therefore, this structure is in favor of the larger memory window (>10 V) design. Random telegraph noise (RTN) characteristics are comparable to the traditional 3-D NAND device with < 0.1-V variation. Excellent single-level cell (SLC) retention with only ~600-mV charge loss after 125 °C one-week high-temperature baking for a post-1K-cycled device was obtained. It is far superior to the control sample without a confined SiN structure. Arrhenius analysis at various baking temperatures shows that the retention may pass>100 years at 60 °C and even longer at room temperature. Moreover, superior post-1K-cycled multilevel cell (MLC) retention was also illustrated, which even sustains 150 °C and one-week baking. Therefore, the device has the potential to meet the low-cost long-retention archive memory applications.]]></description><subject>3-D nand</subject><subject>archive memory</subject><subject>Baking</subject><subject>confined SiN</subject><subject>long retention</subject><subject>Nitrides</subject><subject>Retention</subject><subject>Room temperature</subject><subject>Self alignment</subject><subject>Trapping</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kN9LwzAUhYMoOKfvgi8Bnzvzo82Sx7FuKowqY-JjSZNbl7E1NekG--_t2PDpcuA758KH0CMlI0qJelnN8hEjjIyYElKS7AoNaJaNEyVScY0GhFCZKC75LbqLcdNHkaZsgOwEF_4AWzz1Te0asLhwXXAWklXQbeuaH7zQRwg4h4MzgGsfME9yXEyKHM-3Oq7xt-vWeOmrfezwEjpoOucb_AmhZ3e6MRDv0U2ttxEeLneIvuaz1fQtWXy8vk8ni8QwRbtEcyO5qSm3lilVm9RaJRQ1UoJObUWNsVyoNGMqSzNZCVGZqgYNCogRhDE-RM_n3Tb43z3Ertz4fWj6lyXjQtLeCyc9Rc6UCT7GAHXZBrfT4VhSUp5clr3L8uSyvLjsK0_nigOAf1wqlY3HKf8DsTNvMg</recordid><startdate>20200301</startdate><enddate>20200301</enddate><creator>Fu, Chung-Hao</creator><creator>Lue, Hang-Ting</creator><creator>Hsu, Tzu-Hsuan</creator><creator>Chen, Wei-Chen</creator><creator>Lee, Guan-Ru</creator><creator>Chiu, Chia-Jung</creator><creator>Wang, Keh-Chung</creator><creator>Lu, Chih-Yuan</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-3711-818X</orcidid><orcidid>https://orcid.org/0000-0001-9514-7686</orcidid></search><sort><creationdate>20200301</creationdate><title>A Novel Confined Nitride-Trapping Layer Device for 3-D NAND Flash With Robust Retention Performances</title><author>Fu, Chung-Hao ; Lue, Hang-Ting ; Hsu, Tzu-Hsuan ; Chen, Wei-Chen ; Lee, Guan-Ru ; Chiu, Chia-Jung ; Wang, Keh-Chung ; Lu, Chih-Yuan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c291t-a3c83cf13dd299fc4dd9691c88ea4db1ccd36945295458b66bcbfeae9e0c60223</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2020</creationdate><topic>3-D nand</topic><topic>archive memory</topic><topic>Baking</topic><topic>confined SiN</topic><topic>long retention</topic><topic>Nitrides</topic><topic>Retention</topic><topic>Room temperature</topic><topic>Self alignment</topic><topic>Trapping</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Fu, Chung-Hao</creatorcontrib><creatorcontrib>Lue, Hang-Ting</creatorcontrib><creatorcontrib>Hsu, Tzu-Hsuan</creatorcontrib><creatorcontrib>Chen, Wei-Chen</creatorcontrib><creatorcontrib>Lee, Guan-Ru</creatorcontrib><creatorcontrib>Chiu, Chia-Jung</creatorcontrib><creatorcontrib>Wang, Keh-Chung</creatorcontrib><creatorcontrib>Lu, Chih-Yuan</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics &amp; Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Fu, Chung-Hao</au><au>Lue, Hang-Ting</au><au>Hsu, Tzu-Hsuan</au><au>Chen, Wei-Chen</au><au>Lee, Guan-Ru</au><au>Chiu, Chia-Jung</au><au>Wang, Keh-Chung</au><au>Lu, Chih-Yuan</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A Novel Confined Nitride-Trapping Layer Device for 3-D NAND Flash With Robust Retention Performances</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2020-03-01</date><risdate>2020</risdate><volume>67</volume><issue>3</issue><spage>989</spage><epage>994</epage><pages>989-994</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract><![CDATA[A novel confined nitride (SiN) charge trapping 3-D NAND flash with excellent postcycling retention performances was demonstrated. Using a uniform sidewall lateral recess in the 3-D stack followed by a SiN pull-back process to isolate the SiN trapping layer in a self-aligned way is critical to facilitate this structure. Lower erase saturation < −4 V was shown in the confined SiN cell because of discrete SiN along the <inline-formula> <tex-math notation="LaTeX">{Z} </tex-math></inline-formula>-direction. Therefore, this structure is in favor of the larger memory window (>10 V) design. Random telegraph noise (RTN) characteristics are comparable to the traditional 3-D NAND device with < 0.1-V variation. Excellent single-level cell (SLC) retention with only ~600-mV charge loss after 125 °C one-week high-temperature baking for a post-1K-cycled device was obtained. It is far superior to the control sample without a confined SiN structure. Arrhenius analysis at various baking temperatures shows that the retention may pass>100 years at 60 °C and even longer at room temperature. Moreover, superior post-1K-cycled multilevel cell (MLC) retention was also illustrated, which even sustains 150 °C and one-week baking. Therefore, the device has the potential to meet the low-cost long-retention archive memory applications.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TED.2020.2968805</doi><tpages>6</tpages><orcidid>https://orcid.org/0000-0002-3711-818X</orcidid><orcidid>https://orcid.org/0000-0001-9514-7686</orcidid></addata></record>
fulltext fulltext_linktorsrc
identifier ISSN: 0018-9383
ispartof IEEE transactions on electron devices, 2020-03, Vol.67 (3), p.989-994
issn 0018-9383
1557-9646
language eng
recordid cdi_proquest_journals_2368188030
source IEEE Electronic Library (IEL)
subjects 3-D nand
archive memory
Baking
confined SiN
long retention
Nitrides
Retention
Room temperature
Self alignment
Trapping
title A Novel Confined Nitride-Trapping Layer Device for 3-D NAND Flash With Robust Retention Performances
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-26T07%3A25%3A52IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%20Novel%20Confined%20Nitride-Trapping%20Layer%20Device%20for%203-D%20NAND%20Flash%20With%20Robust%20Retention%20Performances&rft.jtitle=IEEE%20transactions%20on%20electron%20devices&rft.au=Fu,%20Chung-Hao&rft.date=2020-03-01&rft.volume=67&rft.issue=3&rft.spage=989&rft.epage=994&rft.pages=989-994&rft.issn=0018-9383&rft.eissn=1557-9646&rft.coden=IETDAI&rft_id=info:doi/10.1109/TED.2020.2968805&rft_dat=%3Cproquest_RIE%3E2368188030%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2368188030&rft_id=info:pmid/&rft_ieee_id=8995774&rfr_iscdi=true