An up-down topology based-current mode adjustable-gain square-rooting/geometric-mean circuit

A high speed low power current-mode square-rooting/geometric-mean circuit is presented in this paper. The up-down topology with MOS translinear loop in sub-threshold is the basic building block of the proposed circuit which leads to lower supply voltage requirement and body effect issues. This design is also helpful to implement the square-rooting operation of a signal and geometric-mean of two variable signals both with adjustable gain. The performance has been simulated using HSPICE software in 0.18 µm TSMC (level-49 parameters) CMOS technology. Post-layout simulation results with 1-V DC supply voltage show that the maximum linearity error of 1.3%, the − 3 dB bandwidth of 21.9 MHz and maximum power consumption of 700 nW are granted. Monte Carlo analysis is also performed to ensure the stability and robustness of the circuit’s performance in the presence of the PVT (process, voltage and temperature) variations.