A Parasitics-Induced Failure Mechanism for Transistors in the Bit-Line Sense Amplifier Region of DDP DDR3 DRAM During a CDM Event

In the charged-device model (CDM) test, the peak current of the CDM is almost the same if the same package is used. Therefore, it is difficult to understand the reasons for the reduction in the CDM level of double-die package (DDP) DRAM achieved by stacking the same die and package to 30% of that of...

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Veröffentlicht in:	IEEE transactions on device and materials reliability 2019-12, Vol.19 (4), p.711-717
Hauptverfasser:	Lim, Dongju, Seung, Manho, Lee, Yoonsung, Lee, Seokkiu, Kim, Chulwoo
Format:	Magazinearticle
Sprache:	eng
Schlagworte:	Capacitance Charged-device model (CDM) Circuits column-selection line (CSL) transistor Coupling coupling capacitance Critical path double-die package (DDP) Dynamic random access memory Electric potential electrostatic discharge (ESD) Electrostatic discharges Emission analysis Failure analysis Failure mechanisms gate oxide breakdown Immunity Inductance Integrated circuit modeling parasitic inductance Pins Random access memory redistribution layer (RDL) Root cause analysis Semiconductor devices sense amplifier Sense amplifiers single-die package (SDP) Transistors very fast transmission-line pulse (VF-TLP) Voltage
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