General Purpose Readout Board [Formula Omitted]LUP: Overview and Results

The Peripheral Component Interconnect Express (PCIe) Luminosity UPgrade board ([Formula Omitted]LUP) was designed by INFN and University of Bologna as a readout interface candidate to be used after the Phase-II upgrade of the Pixel Detector of the ATLAS and CMS experiments at Large Hadron Collider (LHC). The same team in Bologna is also responsible for the design and commissioning of the readout driver (ROD) board—currently implemented in all the four layers of the ATLAS pixel detector (Insertable B-Layer, B-Layer, Layer-1, and Layer-2)—and acquired in the past years expertise on the ATLAS readout chain and the problematics arising in such experiments. Although the [Formula Omitted]LUP was designed to fulfill a specific task, it is highly versatile and might fit a wide variety of applications, some of which will be discussed in this paper. Two seventh-generation Xilinx field-programmable gate arrays (FPGAs) are mounted on the board: a Zynq-7 with an embedded dual-core Advanced Reduced Instruction Set Computer (RISC) Machine (ARM) Processor and a Kintex-7. The latter features 16 12.5-Gbps transceivers, allowing the board to interface easily to any other electronic board, either electrically and/or optically, at the current bandwidth of the experiments for LHC. Many data-transmission protocols have been tested at different speeds; results will be discussed later in this paper. Two batches of [Formula Omitted]LUP boards have been fabricated and tested; two boards in the first batch (version 1.0) and four boards in the second batch (version 1.1), encapsulating all the patches and improvements required by the first version.