Impact of Complex Logic Cell Layout on the Single-Event Transient Sensitivity

The design methodology based on standard cells is widely used in a broad range of very-large-scale integration (VLSI) applications. Furthermore, several optimization algorithms can be employed to address different constraints such as power consumption or reliability. This paper evaluates the implica...

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Veröffentlicht in:	IEEE transactions on nuclear science 2019-07, Vol.66 (7), p.1465-1472
Hauptverfasser:	Aguiar, Y. Q., Wrobel, F., Autran, J.-L., Leroux, P., Saigne, F., Touboul, A. D., Pouget, V.
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithms Complex logic gate Design standards Electronics Energy transfer Engineering Sciences Field programmable gate arrays Gates (circuits) Heavy ions Integrated circuit modeling Integrated circuits Layout Layouts Libraries Linear energy transfer (LET) Logic Logic circuits Logic gates logical masking Masking Monte Carlo simulation Optimization Power consumption Reduction Reliability analysis Sensitivity single-event transient (SET) Transient analysis Transistors Very large scale integration
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