Design of Protograph-LDPC-Based BICM-ID for Multi-Level-Cell (MLC) NAND Flash Memory
In this letter, the optimization of protograph-low-density parity-check (LDPC)-based bit-interleaved coded modulation with iterative detection and decoding (BICM-ID) with anti-Gray mapping is investigated over multi-level-cell (MLC) NAND flash-memory channels. Since the existing protograph-based ext...
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| Veröffentlicht in: | IEEE communications letters 2019-07, Vol.23 (7), p.1127-1131 |
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| creator | Bu, Yingcheng Fang, Yi Han, Guojun Mumtaz, Shahid Guizani, Mohsen |
| description | In this letter, the optimization of protograph-low-density parity-check (LDPC)-based bit-interleaved coded modulation with iterative detection and decoding (BICM-ID) with anti-Gray mapping is investigated over multi-level-cell (MLC) NAND flash-memory channels. Since the existing protograph-based extrinsic information transfer (PEXIT) algorithm is not applicable to the BICM-ID MLC flash-memory channels, a voltage-sensing PEXIT (VS-PEXIT) algorithm is proposed to facilitate the threshold analysis of protograph codes. Exploiting the proposed VS-PEXIT algorithm, we find that the optimal AR4JA code over AWGN channels cannot preserve its superiority over BICM-ID MLC flash-memory channels. To tackle this problem, we further propose a design scheme to construct a high-rate protograph code, referred to as optimized accumulate-repeat-accumulate (OARA) code , tailored for such scenarios. Theoretical analyses and simulation results illustrate that the proposed OARA-based BICM-ID appears to be an excellent storage scheme over MLC flash-memory channels. |
| doi_str_mv | 10.1109/LCOMM.2019.2915223 |
| format | Article |
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Since the existing protograph-based extrinsic information transfer (PEXIT) algorithm is not applicable to the BICM-ID MLC flash-memory channels, a voltage-sensing PEXIT (VS-PEXIT) algorithm is proposed to facilitate the threshold analysis of protograph codes. Exploiting the proposed VS-PEXIT algorithm, we find that the optimal AR4JA code over AWGN channels cannot preserve its superiority over BICM-ID MLC flash-memory channels. To tackle this problem, we further propose a design scheme to construct a high-rate protograph code, referred to as optimized accumulate-repeat-accumulate (OARA) code , tailored for such scenarios. Theoretical analyses and simulation results illustrate that the proposed OARA-based BICM-ID appears to be an excellent storage scheme over MLC flash-memory channels.</description><identifier>ISSN: 1089-7798</identifier><identifier>EISSN: 1558-2558</identifier><identifier>DOI: 10.1109/LCOMM.2019.2915223</identifier><identifier>CODEN: ICLEF6</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Algorithms ; BICM-ID ; Channels ; Codes ; Computer simulation ; Decoding ; Detectors ; Error correcting codes ; Flash memories ; Flash memory (computers) ; Information transfer ; Iterative decoding ; Mapping ; multi-level-cell NAND flash memory ; Optimization ; Prediction algorithms ; Protograph-based LDPC codes ; Threshold voltage ; VS-PEXIT algorithm</subject><ispartof>IEEE communications letters, 2019-07, Vol.23 (7), p.1127-1131</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2019</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c361t-e9e84bd3a1357685735f03c9e8a3c7ff854e5cad9020652d5bfa65d48f949bf23</citedby><cites>FETCH-LOGICAL-c361t-e9e84bd3a1357685735f03c9e8a3c7ff854e5cad9020652d5bfa65d48f949bf23</cites><orcidid>0000-0001-9483-5276 ; 0000-0002-1538-249X ; 0000-0003-2480-8066 ; 0000-0002-8972-8094 ; 0000-0001-6364-6149</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8708250$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8708250$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Bu, Yingcheng</creatorcontrib><creatorcontrib>Fang, Yi</creatorcontrib><creatorcontrib>Han, Guojun</creatorcontrib><creatorcontrib>Mumtaz, Shahid</creatorcontrib><creatorcontrib>Guizani, Mohsen</creatorcontrib><title>Design of Protograph-LDPC-Based BICM-ID for Multi-Level-Cell (MLC) NAND Flash Memory</title><title>IEEE communications letters</title><addtitle>COML</addtitle><description>In this letter, the optimization of protograph-low-density parity-check (LDPC)-based bit-interleaved coded modulation with iterative detection and decoding (BICM-ID) with anti-Gray mapping is investigated over multi-level-cell (MLC) NAND flash-memory channels. Since the existing protograph-based extrinsic information transfer (PEXIT) algorithm is not applicable to the BICM-ID MLC flash-memory channels, a voltage-sensing PEXIT (VS-PEXIT) algorithm is proposed to facilitate the threshold analysis of protograph codes. Exploiting the proposed VS-PEXIT algorithm, we find that the optimal AR4JA code over AWGN channels cannot preserve its superiority over BICM-ID MLC flash-memory channels. To tackle this problem, we further propose a design scheme to construct a high-rate protograph code, referred to as optimized accumulate-repeat-accumulate (OARA) code , tailored for such scenarios. Theoretical analyses and simulation results illustrate that the proposed OARA-based BICM-ID appears to be an excellent storage scheme over MLC flash-memory channels.</description><subject>Algorithms</subject><subject>BICM-ID</subject><subject>Channels</subject><subject>Codes</subject><subject>Computer simulation</subject><subject>Decoding</subject><subject>Detectors</subject><subject>Error correcting codes</subject><subject>Flash memories</subject><subject>Flash memory (computers)</subject><subject>Information transfer</subject><subject>Iterative decoding</subject><subject>Mapping</subject><subject>multi-level-cell NAND flash memory</subject><subject>Optimization</subject><subject>Prediction algorithms</subject><subject>Protograph-based LDPC codes</subject><subject>Threshold voltage</subject><subject>VS-PEXIT algorithm</subject><issn>1089-7798</issn><issn>1558-2558</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2019</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kMtOwzAQRS0EEqXwA7CxxAYWLn7Eib1sEwqVkraLsrbcxO5DaV3sFKl_T0IrNjOj0b1zNQeAR4IHhGD5lqezohhQTOSASsIpZVegRzgXiLblup2xkChJpLgFdyFsMcaCctIDi8yEzWoPnYVz7xq38vqwRnk2T9FIB1PB0SQt0CSD1nlYHOtmg3LzY2qUmrqGL0WevsLpcJrBca3DGhZm5_zpHtxYXQfzcOl98DV-X6SfKJ99TNJhjkoWkwYZaUS0rJgmjCex4AnjFrOy3WpWJtYKHhle6kpiimNOK760OuZVJKyM5NJS1gfP57sH776PJjRq645-30Yq2v0dC4FFq6JnVeldCN5YdfCbnfYnRbDq6Kk_eqqjpy70WtPT2bQxxvwbRNJhw-wXLR5n2Q</recordid><startdate>20190701</startdate><enddate>20190701</enddate><creator>Bu, Yingcheng</creator><creator>Fang, Yi</creator><creator>Han, Guojun</creator><creator>Mumtaz, Shahid</creator><creator>Guizani, Mohsen</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0001-9483-5276</orcidid><orcidid>https://orcid.org/0000-0002-1538-249X</orcidid><orcidid>https://orcid.org/0000-0003-2480-8066</orcidid><orcidid>https://orcid.org/0000-0002-8972-8094</orcidid><orcidid>https://orcid.org/0000-0001-6364-6149</orcidid></search><sort><creationdate>20190701</creationdate><title>Design of Protograph-LDPC-Based BICM-ID for Multi-Level-Cell (MLC) NAND Flash Memory</title><author>Bu, Yingcheng ; Fang, Yi ; Han, Guojun ; Mumtaz, Shahid ; Guizani, Mohsen</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c361t-e9e84bd3a1357685735f03c9e8a3c7ff854e5cad9020652d5bfa65d48f949bf23</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2019</creationdate><topic>Algorithms</topic><topic>BICM-ID</topic><topic>Channels</topic><topic>Codes</topic><topic>Computer simulation</topic><topic>Decoding</topic><topic>Detectors</topic><topic>Error correcting codes</topic><topic>Flash memories</topic><topic>Flash memory (computers)</topic><topic>Information transfer</topic><topic>Iterative decoding</topic><topic>Mapping</topic><topic>multi-level-cell NAND flash memory</topic><topic>Optimization</topic><topic>Prediction algorithms</topic><topic>Protograph-based LDPC codes</topic><topic>Threshold voltage</topic><topic>VS-PEXIT algorithm</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Bu, Yingcheng</creatorcontrib><creatorcontrib>Fang, Yi</creatorcontrib><creatorcontrib>Han, Guojun</creatorcontrib><creatorcontrib>Mumtaz, Shahid</creatorcontrib><creatorcontrib>Guizani, Mohsen</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE communications letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Bu, Yingcheng</au><au>Fang, Yi</au><au>Han, Guojun</au><au>Mumtaz, Shahid</au><au>Guizani, Mohsen</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Design of Protograph-LDPC-Based BICM-ID for Multi-Level-Cell (MLC) NAND Flash Memory</atitle><jtitle>IEEE communications letters</jtitle><stitle>COML</stitle><date>2019-07-01</date><risdate>2019</risdate><volume>23</volume><issue>7</issue><spage>1127</spage><epage>1131</epage><pages>1127-1131</pages><issn>1089-7798</issn><eissn>1558-2558</eissn><coden>ICLEF6</coden><abstract>In this letter, the optimization of protograph-low-density parity-check (LDPC)-based bit-interleaved coded modulation with iterative detection and decoding (BICM-ID) with anti-Gray mapping is investigated over multi-level-cell (MLC) NAND flash-memory channels. Since the existing protograph-based extrinsic information transfer (PEXIT) algorithm is not applicable to the BICM-ID MLC flash-memory channels, a voltage-sensing PEXIT (VS-PEXIT) algorithm is proposed to facilitate the threshold analysis of protograph codes. Exploiting the proposed VS-PEXIT algorithm, we find that the optimal AR4JA code over AWGN channels cannot preserve its superiority over BICM-ID MLC flash-memory channels. To tackle this problem, we further propose a design scheme to construct a high-rate protograph code, referred to as optimized accumulate-repeat-accumulate (OARA) code , tailored for such scenarios. Theoretical analyses and simulation results illustrate that the proposed OARA-based BICM-ID appears to be an excellent storage scheme over MLC flash-memory channels.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/LCOMM.2019.2915223</doi><tpages>5</tpages><orcidid>https://orcid.org/0000-0001-9483-5276</orcidid><orcidid>https://orcid.org/0000-0002-1538-249X</orcidid><orcidid>https://orcid.org/0000-0003-2480-8066</orcidid><orcidid>https://orcid.org/0000-0002-8972-8094</orcidid><orcidid>https://orcid.org/0000-0001-6364-6149</orcidid></addata></record> |
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| subjects | Algorithms BICM-ID Channels Codes Computer simulation Decoding Detectors Error correcting codes Flash memories Flash memory (computers) Information transfer Iterative decoding Mapping multi-level-cell NAND flash memory Optimization Prediction algorithms Protograph-based LDPC codes Threshold voltage VS-PEXIT algorithm |
| title | Design of Protograph-LDPC-Based BICM-ID for Multi-Level-Cell (MLC) NAND Flash Memory |
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