Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis

Validation and debug challenges of system-on-chips (SoCs) are getting increasingly difficult. As we reach the limits of Dennard scaling, efforts to improve system performance and energy efficiency have resulted in the integration of a wide variety of complex hardware accelerators in SoCs. Hence, it...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems 2019-07, Vol.38 (7), p.1345-1358
Hauptverfasser:	Campbell, Keith, Lin, David, He, Leon, Yang, Liwei, Gurumani, Swathi T., Rupnow, Kyle, Mitra, Subhasish, Chen, Deming
Format:	Artikel
Sprache:	eng
Schlagworte:	Accelerators Automation C++ languages co-simulation Computer bugs debug Debugging detection latency electrical bug Error correction & detection Error detection Hardware High level synthesis high-level synthesis (HLS) hybrid hashing hybrid tracing Integrated circuit modeling logic bug post-silicon presilicon Silicon simulation Software system modeling Testing validation
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