Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks

This article presents Neural Cache architecture, which repurposes cache structures to transform them into massively parallel compute units capable of running inferences for deep neural networks. Techniques to do in situ arithmetic in SRAM arrays create efficient data mapping, and reducing data movem...

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Veröffentlicht in:	IEEE MICRO 2019-05, Vol.39 (3), p.11-19
Hauptverfasser:	Eckert, Charles, Wang, Xiaowei, Wang, Jingcheng, Subramaniyan, Arun, Sylvester, Dennis, Blaauw, David, Das, Reetuparna, Iyer, Ravi
Format:	Artikel
Sprache:	eng
Schlagworte:	Acceleration Arrays Artificial neural networks Computer architecture Convolution Latches Layout Logic arrays Mapping Neural networks Random access memory
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