Hybrid Logical Effort for Hybrid Logic Style Full Adders in Multistage Structures

One of the critical issues in the advancement of very large scale of integration circuit design is the estimation of timing behavior of the arithmetic circuits. The concept of logical effort provides a proficient approach to comprehend and assess the timing behavior of circuits with conventional CMO...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2019-05, Vol.27 (5), p.1138-1147
Hauptverfasser:	basireddy, hareesh-reddy, challa, Karthikeya, Nikoubin, Tooraj
Format:	Artikel
Sprache:	eng
Schlagworte:	Adders Adding circuits Capacitance Circuit design CMOS Delays Drivability Energy management hybrid CMOS hybrid logical effort Hybrid structures input capacitance Integrated circuit modeling Large scale integration Logic gates logical effort Multistage Optimization Portable equipment Power consumption Power management timing behavior Transistors Very large scale
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