A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS
This paper presents a fully differential transimpedance amplifier (TIA) realized in a standard 65-nm CMOS process, where a novel mirrored-cascode (MC) input configuration is proposed for differential signaling, i.e., an NMOS cascode amplifier with a resistive feedback for negative output and its MC...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2019-05, Vol.54 (5), p.1468-1474 |
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| container_title | IEEE journal of solid-state circuits |
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| creator | Kim, Sang Gyun Hong, Chaerin Eo, Yun Seong Kim, Jihoon Park, Sung Min |
| description | This paper presents a fully differential transimpedance amplifier (TIA) realized in a standard 65-nm CMOS process, where a novel mirrored-cascode (MC) input configuration is proposed for differential signaling, i.e., an NMOS cascode amplifier with a resistive feedback for negative output and its MC amplifier via an ac-coupling capacitor for positive output. For bandwidth extension, the third-order asymmetric transformers were carefully employed. Measured results of the proposed MC differential (MCD) TIA demonstrate 54-dB \Omega transimpedance gain, 40-GHz bandwidth for 50-fF photodiode capacitance, 19.8-\text{pA}/\sqrt {\mathrm {Hz}} average noise current spectral density, ±10-ps group delay variation, and 55.2-mW power consumption. Eye diagrams for 32 Gb/s 2 15 -1 pseudo random binary sequence (PRBS) were measured with the input currents of 100-1.5 mApp. The chip occupies the area of 0.6 mm 2 including I/O pads. |
| doi_str_mv | 10.1109/JSSC.2018.2886323 |
| format | Article |
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For bandwidth extension, the third-order asymmetric transformers were carefully employed. Measured results of the proposed MC differential (MCD) TIA demonstrate 54-dB<inline-formula> <tex-math notation="LaTeX">\Omega </tex-math></inline-formula> transimpedance gain, 40-GHz bandwidth for 50-fF photodiode capacitance, <inline-formula> <tex-math notation="LaTeX">19.8-\text{pA}/\sqrt {\mathrm {Hz}} </tex-math></inline-formula> average noise current spectral density, ±10-ps group delay variation, and 55.2-mW power consumption. Eye diagrams for 32 Gb/s 2 15 -1 pseudo random binary sequence (PRBS) were measured with the input currents of 100-1.5 mApp. The chip occupies the area of 0.6 mm 2 including I/O pads.]]></description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2018.2886323</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Amplifiers ; Asymmetric transformers ; Bandwidth ; Capacitance ; Capacitors ; Cascode devices ; CMOS ; Group delay ; Metal oxide semiconductors ; mirrored cascode (MC) ; MOS devices ; Photodiodes ; Power consumption ; Semiconductor device measurement ; single to differential ; transimpedance amplifier (TIA)</subject><ispartof>IEEE journal of solid-state circuits, 2019-05, Vol.54 (5), p.1468-1474</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2019</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c293t-2fc93fd22665ed1f4bdd36f60c6d5f5a31aa8f1110e6a59c0ccaae0ff9acdfa33</citedby><cites>FETCH-LOGICAL-c293t-2fc93fd22665ed1f4bdd36f60c6d5f5a31aa8f1110e6a59c0ccaae0ff9acdfa33</cites><orcidid>0000-0002-1516-2147 ; 0000-0001-9157-6635 ; 0000-0002-9809-1339 ; 0000-0003-2653-9955</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8594639$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8594639$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Kim, Sang Gyun</creatorcontrib><creatorcontrib>Hong, Chaerin</creatorcontrib><creatorcontrib>Eo, Yun Seong</creatorcontrib><creatorcontrib>Kim, Jihoon</creatorcontrib><creatorcontrib>Park, Sung Min</creatorcontrib><title>A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description><![CDATA[This paper presents a fully differential transimpedance amplifier (TIA) realized in a standard 65-nm CMOS process, where a novel mirrored-cascode (MC) input configuration is proposed for differential signaling, i.e., an NMOS cascode amplifier with a resistive feedback for negative output and its MC amplifier via an ac-coupling capacitor for positive output. For bandwidth extension, the third-order asymmetric transformers were carefully employed. Measured results of the proposed MC differential (MCD) TIA demonstrate 54-dB<inline-formula> <tex-math notation="LaTeX">\Omega </tex-math></inline-formula> transimpedance gain, 40-GHz bandwidth for 50-fF photodiode capacitance, <inline-formula> <tex-math notation="LaTeX">19.8-\text{pA}/\sqrt {\mathrm {Hz}} </tex-math></inline-formula> average noise current spectral density, ±10-ps group delay variation, and 55.2-mW power consumption. Eye diagrams for 32 Gb/s 2 15 -1 pseudo random binary sequence (PRBS) were measured with the input currents of 100-1.5 mApp. The chip occupies the area of 0.6 mm 2 including I/O pads.]]></description><subject>Amplifiers</subject><subject>Asymmetric transformers</subject><subject>Bandwidth</subject><subject>Capacitance</subject><subject>Capacitors</subject><subject>Cascode devices</subject><subject>CMOS</subject><subject>Group delay</subject><subject>Metal oxide semiconductors</subject><subject>mirrored cascode (MC)</subject><subject>MOS devices</subject><subject>Photodiodes</subject><subject>Power consumption</subject><subject>Semiconductor device measurement</subject><subject>single to differential</subject><subject>transimpedance amplifier (TIA)</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2019</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kE1LAzEQhoMoWKs_QLwEPKfmY5NujmXVVmnpoRW8hZhMIKX7YbI96K93S4unYZjnnWEehO4ZnTBG9dP7ZlNNOGXlhJelElxcoBGTsiRsKj4v0YgOI6I5pdfoJufd0BZFyUZoNcMFJfPFL17FlNoEnlQ2u9YDfo4hQIKmj3aPt8k2OdYdeNs4wLO628cQIeHYYCVJU-Nqtd7coqtg9xnuznWMPl5fttWCLNfzt2q2JI5r0RMenBbBc66UBM9C8eW9UEFRp7wM0gpmbRnY8BgoK7WjzlkLNARtnQ9WiDF6PO3tUvt9gNybXXtIzXDScM4knU45UwPFTpRLbc4JgulSrG36MYyaozVztGaO1szZ2pB5OGUiAPzzpdSFElr8AXJOZ-A</recordid><startdate>20190501</startdate><enddate>20190501</enddate><creator>Kim, Sang Gyun</creator><creator>Hong, Chaerin</creator><creator>Eo, Yun Seong</creator><creator>Kim, Jihoon</creator><creator>Park, Sung Min</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Amplifiers Asymmetric transformers Bandwidth Capacitance Capacitors Cascode devices CMOS Group delay Metal oxide semiconductors mirrored cascode (MC) MOS devices Photodiodes Power consumption Semiconductor device measurement single to differential transimpedance amplifier (TIA) |
| title | A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS |
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