High-Volume Testing and DC Offset Trimming Technique of On-Die Bandgap Voltage Reference for SOCs and Microprocessors
Since the VLSI chips were invented, as predicted by Moore's law, the performance, the power, and the cost of the VLSI chips have been improved, which brought a significant benefit to the economy. However, some of the analog circuits do not get a full benefit from the scaling, due to the increas...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2019-04, Vol.27 (4), p.821-829 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | Oshita, Takao Douglas, Jonathan Krishnamoorthy, Arun |
| description | Since the VLSI chips were invented, as predicted by Moore's law, the performance, the power, and the cost of the VLSI chips have been improved, which brought a significant benefit to the economy. However, some of the analog circuits do not get a full benefit from the scaling, due to the increased device variability with transistors in smaller dimension. Under such circumstance, the calibration and trimming techniques are essential to overcome the sensitivity to the process variation. This paper presents the trimming technique to correct the direct current (dc) offset error of the bandgap voltage reference circuit, which complies with the high-volume manufacturing (HVM) requirements. The proposed trimming method consists of the combination of two different sequences, the coarse and fine trimming. The accuracy of the dc offset trimming is evaluated by the newly invented method that complies with the HVM requirements. With a compact silicon area of only 700 \mu \text{m}^{2} , the dc offset trimming circuit achieved an accuracy of ±5 mV ( 4\sigma ) as a result of the coarse and fine trimming operations. |
| doi_str_mv | 10.1109/TVLSI.2018.2882567 |
| format | Article |
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However, some of the analog circuits do not get a full benefit from the scaling, due to the increased device variability with transistors in smaller dimension. Under such circumstance, the calibration and trimming techniques are essential to overcome the sensitivity to the process variation. This paper presents the trimming technique to correct the direct current (dc) offset error of the bandgap voltage reference circuit, which complies with the high-volume manufacturing (HVM) requirements. The proposed trimming method consists of the combination of two different sequences, the coarse and fine trimming. The accuracy of the dc offset trimming is evaluated by the newly invented method that complies with the HVM requirements. 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(IEEE) 2019</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c361t-d6097a82d8e2dcc33a8a94be5a281cee0d25d1dd8b676af3b6ef15c8cb93864a3</citedby><cites>FETCH-LOGICAL-c361t-d6097a82d8e2dcc33a8a94be5a281cee0d25d1dd8b676af3b6ef15c8cb93864a3</cites><orcidid>0000-0001-8060-0118</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8573820$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27922,27923,54756</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8573820$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Oshita, Takao</creatorcontrib><creatorcontrib>Douglas, Jonathan</creatorcontrib><creatorcontrib>Krishnamoorthy, Arun</creatorcontrib><title>High-Volume Testing and DC Offset Trimming Technique of On-Die Bandgap Voltage Reference for SOCs and Microprocessors</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description><![CDATA[Since the VLSI chips were invented, as predicted by Moore's law, the performance, the power, and the cost of the VLSI chips have been improved, which brought a significant benefit to the economy. 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| ispartof | IEEE transactions on very large scale integration (VLSI) systems, 2019-04, Vol.27 (4), p.821-829 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Analog circuits Bandgap voltage reference design for testability Direct current direct current (dc) offset trimming Discrete Fourier transforms Electric potential Energy gap Error correction Hardware high-volume manufacturing (HVM) Integrated circuits Microprocessors Photonic band gap Production Semiconductor devices Silicon system on chip (SOC) Testing Transistors Trimming Very large scale integration Voltage measurement |
| title | High-Volume Testing and DC Offset Trimming Technique of On-Die Bandgap Voltage Reference for SOCs and Microprocessors |
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