Using an optimized queueing network model to support wafer fab design

We develop an Optimized Queueing Network (OQNet) capacity planning tool for supporting the design of new and reconfigured semiconductor fabrication facilities that makes use of queueing network approximations and an optimization routine. The basic problem addressed by this tool is to minimize the fa...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IIE transactions 2002-02, Vol.34 (2), p.119-130
Hauptverfasser: HOPP, WALLACE J., SPEARMAN, MARK L., CHAYET, SERGIO, DONOHUE, KAREN L., GEL, ESMA S.
Format: Artikel
Sprache:eng
Schlagworte:
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 130
container_issue 2
container_start_page 119
container_title IIE transactions
container_volume 34
creator HOPP, WALLACE J.
SPEARMAN, MARK L.
CHAYET, SERGIO
DONOHUE, KAREN L.
GEL, ESMA S.
description We develop an Optimized Queueing Network (OQNet) capacity planning tool for supporting the design of new and reconfigured semiconductor fabrication facilities that makes use of queueing network approximations and an optimization routine. The basic problem addressed by this tool is to minimize the facility cost required to meet specified volume and cycle time targets. Features common to semiconductor environments, such as batch processes, re-entrant flows, multiple product classes, and machine setups, are incorporated into the model. Comparisons with simulation show that the queueing and other approximations are reasonably accurate. Tests of the optimization routine demonstrate that it can find good solutions quickly.
doi_str_mv 10.1080/07408170208928855
format Article
fullrecord <record><control><sourceid>proquest_infor</sourceid><recordid>TN_cdi_proquest_journals_219688337</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>109375022</sourcerecordid><originalsourceid>FETCH-LOGICAL-c373t-f9759c192c577b50de11aff9a854ee0bbcffe4b49bb5e761e9d14251ee52ae4e3</originalsourceid><addsrcrecordid>eNqFkE9LxDAQxYMouK5-AG_Be3XSNpsEvMiy_oEFLy54C2k7Wbq2TU1S1vXT22W9LehpYGZ-8-Y9Qq4Z3DKQcAciB8kEpCBVKiXnJ2TCeM4TKTM4JZP9PBkX3s_JRQgbABDA5IQsVqHu1tR01PWxbutvrOjngAPuux3GrfMftHUVNjQ6Goa-dz7SrbHoqTUFrTDU6-6SnFnTBLz6rVOyely8zZ-T5evTy_xhmZSZyGJileCqZCotuRAFhwoZM9YqI3mOCEVRWot5kaui4ChmDFXF8pQzRJ4azDGbkpvD3d678csQ9cYNvhsldcrUbPQ66kwJOyyV3oXg0ere163xO81A78PSR2GNzP2BqTvrfGtG202lo9k1zltvurIOOvsLF__iR5SOXzH7AZT2gng</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>219688337</pqid></control><display><type>article</type><title>Using an optimized queueing network model to support wafer fab design</title><source>Access via Taylor &amp; Francis</source><source>Business Source Complete</source><source>Alma/SFX Local Collection</source><creator>HOPP, WALLACE J. ; SPEARMAN, MARK L. ; CHAYET, SERGIO ; DONOHUE, KAREN L. ; GEL, ESMA S.</creator><creatorcontrib>HOPP, WALLACE J. ; SPEARMAN, MARK L. ; CHAYET, SERGIO ; DONOHUE, KAREN L. ; GEL, ESMA S.</creatorcontrib><description>We develop an Optimized Queueing Network (OQNet) capacity planning tool for supporting the design of new and reconfigured semiconductor fabrication facilities that makes use of queueing network approximations and an optimization routine. The basic problem addressed by this tool is to minimize the facility cost required to meet specified volume and cycle time targets. Features common to semiconductor environments, such as batch processes, re-entrant flows, multiple product classes, and machine setups, are incorporated into the model. Comparisons with simulation show that the queueing and other approximations are reasonably accurate. Tests of the optimization routine demonstrate that it can find good solutions quickly.</description><identifier>ISSN: 0740-817X</identifier><identifier>ISSN: 2472-5854</identifier><identifier>EISSN: 1545-8830</identifier><identifier>EISSN: 2472-5862</identifier><identifier>DOI: 10.1080/07408170208928855</identifier><identifier>CODEN: IIETDM</identifier><language>eng</language><publisher>Norcross: Taylor &amp; Francis Group</publisher><subject>Algorithms ; Approximation ; Batch processes ; Batch processing ; Decision making ; Design engineering ; Management science ; Manufacturing ; Mathematical models ; Network management systems ; Optimization ; Production planning ; Queuing theory ; Semiconductors ; Simulation ; Studies</subject><ispartof>IIE transactions, 2002-02, Vol.34 (2), p.119-130</ispartof><rights>Copyright Taylor &amp; Francis Group, LLC 2002</rights><rights>Copyright Institute of Industrial Engineers Feb 2002</rights><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c373t-f9759c192c577b50de11aff9a854ee0bbcffe4b49bb5e761e9d14251ee52ae4e3</citedby><cites>FETCH-LOGICAL-c373t-f9759c192c577b50de11aff9a854ee0bbcffe4b49bb5e761e9d14251ee52ae4e3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://www.tandfonline.com/doi/pdf/10.1080/07408170208928855$$EPDF$$P50$$Ginformaworld$$H</linktopdf><linktohtml>$$Uhttps://www.tandfonline.com/doi/full/10.1080/07408170208928855$$EHTML$$P50$$Ginformaworld$$H</linktohtml><link.rule.ids>315,781,785,27929,27930,59652,60441</link.rule.ids></links><search><creatorcontrib>HOPP, WALLACE J.</creatorcontrib><creatorcontrib>SPEARMAN, MARK L.</creatorcontrib><creatorcontrib>CHAYET, SERGIO</creatorcontrib><creatorcontrib>DONOHUE, KAREN L.</creatorcontrib><creatorcontrib>GEL, ESMA S.</creatorcontrib><title>Using an optimized queueing network model to support wafer fab design</title><title>IIE transactions</title><description>We develop an Optimized Queueing Network (OQNet) capacity planning tool for supporting the design of new and reconfigured semiconductor fabrication facilities that makes use of queueing network approximations and an optimization routine. The basic problem addressed by this tool is to minimize the facility cost required to meet specified volume and cycle time targets. Features common to semiconductor environments, such as batch processes, re-entrant flows, multiple product classes, and machine setups, are incorporated into the model. Comparisons with simulation show that the queueing and other approximations are reasonably accurate. Tests of the optimization routine demonstrate that it can find good solutions quickly.</description><subject>Algorithms</subject><subject>Approximation</subject><subject>Batch processes</subject><subject>Batch processing</subject><subject>Decision making</subject><subject>Design engineering</subject><subject>Management science</subject><subject>Manufacturing</subject><subject>Mathematical models</subject><subject>Network management systems</subject><subject>Optimization</subject><subject>Production planning</subject><subject>Queuing theory</subject><subject>Semiconductors</subject><subject>Simulation</subject><subject>Studies</subject><issn>0740-817X</issn><issn>2472-5854</issn><issn>1545-8830</issn><issn>2472-5862</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2002</creationdate><recordtype>article</recordtype><recordid>eNqFkE9LxDAQxYMouK5-AG_Be3XSNpsEvMiy_oEFLy54C2k7Wbq2TU1S1vXT22W9LehpYGZ-8-Y9Qq4Z3DKQcAciB8kEpCBVKiXnJ2TCeM4TKTM4JZP9PBkX3s_JRQgbABDA5IQsVqHu1tR01PWxbutvrOjngAPuux3GrfMftHUVNjQ6Goa-dz7SrbHoqTUFrTDU6-6SnFnTBLz6rVOyely8zZ-T5evTy_xhmZSZyGJileCqZCotuRAFhwoZM9YqI3mOCEVRWot5kaui4ChmDFXF8pQzRJ4azDGbkpvD3d678csQ9cYNvhsldcrUbPQ66kwJOyyV3oXg0ere163xO81A78PSR2GNzP2BqTvrfGtG202lo9k1zltvurIOOvsLF__iR5SOXzH7AZT2gng</recordid><startdate>20020201</startdate><enddate>20020201</enddate><creator>HOPP, WALLACE J.</creator><creator>SPEARMAN, MARK L.</creator><creator>CHAYET, SERGIO</creator><creator>DONOHUE, KAREN L.</creator><creator>GEL, ESMA S.</creator><general>Taylor &amp; Francis Group</general><general>Taylor &amp; Francis Ltd</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7TB</scope><scope>8FD</scope><scope>FR3</scope></search><sort><creationdate>20020201</creationdate><title>Using an optimized queueing network model to support wafer fab design</title><author>HOPP, WALLACE J. ; SPEARMAN, MARK L. ; CHAYET, SERGIO ; DONOHUE, KAREN L. ; GEL, ESMA S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c373t-f9759c192c577b50de11aff9a854ee0bbcffe4b49bb5e761e9d14251ee52ae4e3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2002</creationdate><topic>Algorithms</topic><topic>Approximation</topic><topic>Batch processes</topic><topic>Batch processing</topic><topic>Decision making</topic><topic>Design engineering</topic><topic>Management science</topic><topic>Manufacturing</topic><topic>Mathematical models</topic><topic>Network management systems</topic><topic>Optimization</topic><topic>Production planning</topic><topic>Queuing theory</topic><topic>Semiconductors</topic><topic>Simulation</topic><topic>Studies</topic><toplevel>online_resources</toplevel><creatorcontrib>HOPP, WALLACE J.</creatorcontrib><creatorcontrib>SPEARMAN, MARK L.</creatorcontrib><creatorcontrib>CHAYET, SERGIO</creatorcontrib><creatorcontrib>DONOHUE, KAREN L.</creatorcontrib><creatorcontrib>GEL, ESMA S.</creatorcontrib><collection>CrossRef</collection><collection>Mechanical &amp; Transportation Engineering Abstracts</collection><collection>Technology Research Database</collection><collection>Engineering Research Database</collection><jtitle>IIE transactions</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>HOPP, WALLACE J.</au><au>SPEARMAN, MARK L.</au><au>CHAYET, SERGIO</au><au>DONOHUE, KAREN L.</au><au>GEL, ESMA S.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Using an optimized queueing network model to support wafer fab design</atitle><jtitle>IIE transactions</jtitle><date>2002-02-01</date><risdate>2002</risdate><volume>34</volume><issue>2</issue><spage>119</spage><epage>130</epage><pages>119-130</pages><issn>0740-817X</issn><issn>2472-5854</issn><eissn>1545-8830</eissn><eissn>2472-5862</eissn><coden>IIETDM</coden><abstract>We develop an Optimized Queueing Network (OQNet) capacity planning tool for supporting the design of new and reconfigured semiconductor fabrication facilities that makes use of queueing network approximations and an optimization routine. The basic problem addressed by this tool is to minimize the facility cost required to meet specified volume and cycle time targets. Features common to semiconductor environments, such as batch processes, re-entrant flows, multiple product classes, and machine setups, are incorporated into the model. Comparisons with simulation show that the queueing and other approximations are reasonably accurate. Tests of the optimization routine demonstrate that it can find good solutions quickly.</abstract><cop>Norcross</cop><pub>Taylor &amp; Francis Group</pub><doi>10.1080/07408170208928855</doi><tpages>12</tpages></addata></record>
fulltext fulltext
identifier ISSN: 0740-817X
ispartof IIE transactions, 2002-02, Vol.34 (2), p.119-130
issn 0740-817X
2472-5854
1545-8830
2472-5862
language eng
recordid cdi_proquest_journals_219688337
source Access via Taylor & Francis; Business Source Complete; Alma/SFX Local Collection
subjects Algorithms
Approximation
Batch processes
Batch processing
Decision making
Design engineering
Management science
Manufacturing
Mathematical models
Network management systems
Optimization
Production planning
Queuing theory
Semiconductors
Simulation
Studies
title Using an optimized queueing network model to support wafer fab design
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-13T18%3A58%3A37IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_infor&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Using%20an%20optimized%20queueing%20network%20model%20to%20support%20wafer%20fab%20design&rft.jtitle=IIE%20transactions&rft.au=HOPP,%20WALLACE%20J.&rft.date=2002-02-01&rft.volume=34&rft.issue=2&rft.spage=119&rft.epage=130&rft.pages=119-130&rft.issn=0740-817X&rft.eissn=1545-8830&rft.coden=IIETDM&rft_id=info:doi/10.1080/07408170208928855&rft_dat=%3Cproquest_infor%3E109375022%3C/proquest_infor%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=219688337&rft_id=info:pmid/&rfr_iscdi=true