Turn-Off Transient of Superjunction SOI Lateral IGBTs: Mechanism and Optimization Strategy
In this paper, five types of superjunction (SJ) configurations are investigated in the silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT). technology computer aided design simulations are carried out to give insight into the mechanism for improving turn-off loss ( {E} _{ \mat...
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Veröffentlicht in: | IEEE transactions on electron devices 2019-03, Vol.66 (3), p.1409-1415 |
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creator | Zhang, Long Zhu, Jing Ma, Jie Cao, Shilin Li, Ankang Li, Shaohong Ye, Ran Sun, Weifeng Zhao, Jianfeng Shi, Longxing |
description | In this paper, five types of superjunction (SJ) configurations are investigated in the silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT). technology computer aided design simulations are carried out to give insight into the mechanism for improving turn-off loss ( {E} _{ \mathrm{\scriptscriptstyle OFF}} ) by adopting SJ in the drift region of SOI-LIGBT. In mechanism revealing, collector-emitter voltage rising during the inductive load turn-off is divided into two phases: slow rising phase (SRP) and rapid rising phase (RRP). It is found that the depletion accompanying with carrier extraction in the drift region and at the collector is responsible for the SRP and RRP, respectively, and accordingly, the difference of turn-off transient among the five types of SJ configurations is clarified. Moreover, reduced {E} _{ \mathrm{\scriptscriptstyle OFF}} can be realized by lowering the transition voltage from SRP to RRP ( {V} _{\text {A}} ). Low electric potential from the emitter side can be delivered to the collector side through the undepleted regions in P-pillar, which largely determine {V} _{\text {A}} . According to the above-mentioned mechanism, an optimization strategy and a novel SJ SOI-LIGBT with composite P-pillar are proposed for the first time. The proposed SJ SOI-LIGBT achieves an {E} _{ \mathrm{\scriptscriptstyle OFF}}~76.3 % lower than the conventional SOI-LIGBT at ON-state voltage drop of ~1.41 V. |
doi_str_mv | 10.1109/TED.2019.2894813 |
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In mechanism revealing, collector-emitter voltage rising during the inductive load turn-off is divided into two phases: slow rising phase (SRP) and rapid rising phase (RRP). It is found that the depletion accompanying with carrier extraction in the drift region and at the collector is responsible for the SRP and RRP, respectively, and accordingly, the difference of turn-off transient among the five types of SJ configurations is clarified. Moreover, reduced <inline-formula> <tex-math notation="LaTeX">{E} _{ \mathrm{\scriptscriptstyle OFF}} </tex-math></inline-formula> can be realized by lowering the transition voltage from SRP to RRP (<inline-formula> <tex-math notation="LaTeX">{V} _{\text {A}} </tex-math></inline-formula>). Low electric potential from the emitter side can be delivered to the collector side through the undepleted regions in P-pillar, which largely determine <inline-formula> <tex-math notation="LaTeX">{V} _{\text {A}} </tex-math></inline-formula>. According to the above-mentioned mechanism, an optimization strategy and a novel SJ SOI-LIGBT with composite P-pillar are proposed for the first time. The proposed SJ SOI-LIGBT achieves an <inline-formula> <tex-math notation="LaTeX">{E} _{ \mathrm{\scriptscriptstyle OFF}}~76.3 </tex-math></inline-formula>% lower than the conventional SOI-LIGBT at ON-state voltage drop of ~1.41 V.]]></description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2019.2894813</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Breakdown voltage (BV) ; CAD ; Computer aided design ; Computer simulation ; Configurations ; Depletion ; Doping ; Drift ; Electric potential ; Emitters ; fast turn-off ; high speed ; Insulated gate bipolar transistors ; Integrated circuit modeling ; Load modeling ; ON-state voltage drop (<italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">V ₒₙ) ; Optimization ; saturation voltage ; Semiconductor process modeling ; semisuperjunction (semi-SJ) ; Silicon-on-insulator ; silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT) ; SOI (semiconductors) ; stored carriers ; superjunction (SJ) ; tradeoff ; Transient analysis ; turn-off loss (<italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">E OFF) ; Voltage drop</subject><ispartof>IEEE transactions on electron devices, 2019-03, Vol.66 (3), p.1409-1415</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2019</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c357t-5b0dcd981005592e0f8220d977f5ec4c6e9273ac0ae58ef973ec13615ab67e303</citedby><cites>FETCH-LOGICAL-c357t-5b0dcd981005592e0f8220d977f5ec4c6e9273ac0ae58ef973ec13615ab67e303</cites><orcidid>0000-0002-3289-8877 ; 0000-0003-4891-7304 ; 0000-0003-0254-6085</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8637045$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8637045$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Zhang, Long</creatorcontrib><creatorcontrib>Zhu, Jing</creatorcontrib><creatorcontrib>Ma, Jie</creatorcontrib><creatorcontrib>Cao, Shilin</creatorcontrib><creatorcontrib>Li, Ankang</creatorcontrib><creatorcontrib>Li, Shaohong</creatorcontrib><creatorcontrib>Ye, Ran</creatorcontrib><creatorcontrib>Sun, Weifeng</creatorcontrib><creatorcontrib>Zhao, Jianfeng</creatorcontrib><creatorcontrib>Shi, Longxing</creatorcontrib><title>Turn-Off Transient of Superjunction SOI Lateral IGBTs: Mechanism and Optimization Strategy</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description><![CDATA[In this paper, five types of superjunction (SJ) configurations are investigated in the silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT). technology computer aided design simulations are carried out to give insight into the mechanism for improving turn-off loss (<inline-formula> <tex-math notation="LaTeX">{E} _{ \mathrm{\scriptscriptstyle OFF}} </tex-math></inline-formula>) by adopting SJ in the drift region of SOI-LIGBT. In mechanism revealing, collector-emitter voltage rising during the inductive load turn-off is divided into two phases: slow rising phase (SRP) and rapid rising phase (RRP). It is found that the depletion accompanying with carrier extraction in the drift region and at the collector is responsible for the SRP and RRP, respectively, and accordingly, the difference of turn-off transient among the five types of SJ configurations is clarified. Moreover, reduced <inline-formula> <tex-math notation="LaTeX">{E} _{ \mathrm{\scriptscriptstyle OFF}} </tex-math></inline-formula> can be realized by lowering the transition voltage from SRP to RRP (<inline-formula> <tex-math notation="LaTeX">{V} _{\text {A}} </tex-math></inline-formula>). Low electric potential from the emitter side can be delivered to the collector side through the undepleted regions in P-pillar, which largely determine <inline-formula> <tex-math notation="LaTeX">{V} _{\text {A}} </tex-math></inline-formula>. According to the above-mentioned mechanism, an optimization strategy and a novel SJ SOI-LIGBT with composite P-pillar are proposed for the first time. The proposed SJ SOI-LIGBT achieves an <inline-formula> <tex-math notation="LaTeX">{E} _{ \mathrm{\scriptscriptstyle OFF}}~76.3 </tex-math></inline-formula>% lower than the conventional SOI-LIGBT at ON-state voltage drop of ~1.41 V.]]></description><subject>Breakdown voltage (BV)</subject><subject>CAD</subject><subject>Computer aided design</subject><subject>Computer simulation</subject><subject>Configurations</subject><subject>Depletion</subject><subject>Doping</subject><subject>Drift</subject><subject>Electric potential</subject><subject>Emitters</subject><subject>fast turn-off</subject><subject>high speed</subject><subject>Insulated gate bipolar transistors</subject><subject>Integrated circuit modeling</subject><subject>Load modeling</subject><subject>ON-state voltage drop (<italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">V ₒₙ)</subject><subject>Optimization</subject><subject>saturation voltage</subject><subject>Semiconductor process modeling</subject><subject>semisuperjunction (semi-SJ)</subject><subject>Silicon-on-insulator</subject><subject>silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT)</subject><subject>SOI (semiconductors)</subject><subject>stored carriers</subject><subject>superjunction (SJ)</subject><subject>tradeoff</subject><subject>Transient analysis</subject><subject>turn-off loss (<italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">E OFF)</subject><subject>Voltage drop</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2019</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kE1Lw0AQhhdRsFbvgpcFz6n7kf3yprXWQiWHxouXsN3MakqbxN3kUH-9KS2ehoHnfYd5ELqlZEIpMQ_57GXCCDUTpk2qKT9DIyqESoxM5TkaEUJ1Yrjml-gqxs2wyjRlI_SZ96FOMu9xHmwdK6g73Hi86lsIm752XdXUeJUt8NJ2EOwWL-bPeXzE7-C-bV3FHbZ1ibO2q3bVrz3SXRjYr_01uvB2G-HmNMfo43WWT9-SZTZfTJ-WieNCdYlYk9KVRlNChDAMiNeMkdIo5QW41EkwTHHriAWhwRvFwVEuqbBrqYATPkb3x942ND89xK7YNMNTw8mCUS0Up0yagSJHyoUmxgC-aEO1s2FfUFIcDBaDweJgsDgZHCJ3x0gFAP-4llyRVPA_axxrwQ</recordid><startdate>20190301</startdate><enddate>20190301</enddate><creator>Zhang, Long</creator><creator>Zhu, Jing</creator><creator>Ma, Jie</creator><creator>Cao, Shilin</creator><creator>Li, Ankang</creator><creator>Li, Shaohong</creator><creator>Ye, Ran</creator><creator>Sun, Weifeng</creator><creator>Zhao, Jianfeng</creator><creator>Shi, Longxing</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-3289-8877</orcidid><orcidid>https://orcid.org/0000-0003-4891-7304</orcidid><orcidid>https://orcid.org/0000-0003-0254-6085</orcidid></search><sort><creationdate>20190301</creationdate><title>Turn-Off Transient of Superjunction SOI Lateral IGBTs: Mechanism and Optimization Strategy</title><author>Zhang, Long ; Zhu, Jing ; Ma, Jie ; Cao, Shilin ; Li, Ankang ; Li, Shaohong ; Ye, Ran ; Sun, Weifeng ; Zhao, Jianfeng ; Shi, Longxing</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c357t-5b0dcd981005592e0f8220d977f5ec4c6e9273ac0ae58ef973ec13615ab67e303</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2019</creationdate><topic>Breakdown voltage (BV)</topic><topic>CAD</topic><topic>Computer aided design</topic><topic>Computer simulation</topic><topic>Configurations</topic><topic>Depletion</topic><topic>Doping</topic><topic>Drift</topic><topic>Electric potential</topic><topic>Emitters</topic><topic>fast turn-off</topic><topic>high speed</topic><topic>Insulated gate bipolar transistors</topic><topic>Integrated circuit modeling</topic><topic>Load modeling</topic><topic>ON-state voltage drop (<italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">V ₒₙ)</topic><topic>Optimization</topic><topic>saturation voltage</topic><topic>Semiconductor process modeling</topic><topic>semisuperjunction (semi-SJ)</topic><topic>Silicon-on-insulator</topic><topic>silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT)</topic><topic>SOI (semiconductors)</topic><topic>stored carriers</topic><topic>superjunction (SJ)</topic><topic>tradeoff</topic><topic>Transient analysis</topic><topic>turn-off loss (<italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">E OFF)</topic><topic>Voltage drop</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Zhang, Long</creatorcontrib><creatorcontrib>Zhu, Jing</creatorcontrib><creatorcontrib>Ma, Jie</creatorcontrib><creatorcontrib>Cao, Shilin</creatorcontrib><creatorcontrib>Li, Ankang</creatorcontrib><creatorcontrib>Li, Shaohong</creatorcontrib><creatorcontrib>Ye, Ran</creatorcontrib><creatorcontrib>Sun, Weifeng</creatorcontrib><creatorcontrib>Zhao, Jianfeng</creatorcontrib><creatorcontrib>Shi, Longxing</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Zhang, Long</au><au>Zhu, Jing</au><au>Ma, Jie</au><au>Cao, Shilin</au><au>Li, Ankang</au><au>Li, Shaohong</au><au>Ye, Ran</au><au>Sun, Weifeng</au><au>Zhao, Jianfeng</au><au>Shi, Longxing</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Turn-Off Transient of Superjunction SOI Lateral IGBTs: Mechanism and Optimization Strategy</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2019-03-01</date><risdate>2019</risdate><volume>66</volume><issue>3</issue><spage>1409</spage><epage>1415</epage><pages>1409-1415</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract><![CDATA[In this paper, five types of superjunction (SJ) configurations are investigated in the silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT). technology computer aided design simulations are carried out to give insight into the mechanism for improving turn-off loss (<inline-formula> <tex-math notation="LaTeX">{E} _{ \mathrm{\scriptscriptstyle OFF}} </tex-math></inline-formula>) by adopting SJ in the drift region of SOI-LIGBT. In mechanism revealing, collector-emitter voltage rising during the inductive load turn-off is divided into two phases: slow rising phase (SRP) and rapid rising phase (RRP). It is found that the depletion accompanying with carrier extraction in the drift region and at the collector is responsible for the SRP and RRP, respectively, and accordingly, the difference of turn-off transient among the five types of SJ configurations is clarified. Moreover, reduced <inline-formula> <tex-math notation="LaTeX">{E} _{ \mathrm{\scriptscriptstyle OFF}} </tex-math></inline-formula> can be realized by lowering the transition voltage from SRP to RRP (<inline-formula> <tex-math notation="LaTeX">{V} _{\text {A}} </tex-math></inline-formula>). Low electric potential from the emitter side can be delivered to the collector side through the undepleted regions in P-pillar, which largely determine <inline-formula> <tex-math notation="LaTeX">{V} _{\text {A}} </tex-math></inline-formula>. According to the above-mentioned mechanism, an optimization strategy and a novel SJ SOI-LIGBT with composite P-pillar are proposed for the first time. The proposed SJ SOI-LIGBT achieves an <inline-formula> <tex-math notation="LaTeX">{E} _{ \mathrm{\scriptscriptstyle OFF}}~76.3 </tex-math></inline-formula>% lower than the conventional SOI-LIGBT at ON-state voltage drop of ~1.41 V.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TED.2019.2894813</doi><tpages>7</tpages><orcidid>https://orcid.org/0000-0002-3289-8877</orcidid><orcidid>https://orcid.org/0000-0003-4891-7304</orcidid><orcidid>https://orcid.org/0000-0003-0254-6085</orcidid></addata></record> |
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subjects | Breakdown voltage (BV) CAD Computer aided design Computer simulation Configurations Depletion Doping Drift Electric potential Emitters fast turn-off high speed Insulated gate bipolar transistors Integrated circuit modeling Load modeling ON-state voltage drop (<italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">V ₒₙ) Optimization saturation voltage Semiconductor process modeling semisuperjunction (semi-SJ) Silicon-on-insulator silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT) SOI (semiconductors) stored carriers superjunction (SJ) tradeoff Transient analysis turn-off loss (<italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">E OFF) Voltage drop |
title | Turn-Off Transient of Superjunction SOI Lateral IGBTs: Mechanism and Optimization Strategy |
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