An 88-fJ/40-MHz [0.4 V]–0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 [Formula Omitted] 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI

The unique ability of dual-mode logic (DML) to self-adapt to computational needs by providing high speed and/or low energy consumption is demonstrated for the first time by silicon measurements in 28-nm fully depleted silicon on insulator. At the gate level, the DML design offers the possibility to...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2019-02, Vol.54 (2), p.560
Hauptverfasser:	Taco, Ramiro, Levi, Itamar, Lanuzza, Marco, Fish, Alexander
Format:	Artikel
Sprache:	eng
Schlagworte:	Accumulators CMOS Energy conservation Energy consumption Gates (circuits) Run time (computers) Silicon SOI (semiconductors)
Online-Zugang:	Volltext
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