Low-Frequency Noise and Offset Rejection in DC-Coupled Neural Amplifiers: A Review and Digitally-Assisted Design Tutorial

We review integrated circuits for low-frequency noise and offset rejection as a motivation for the presented digitally-assisted neural amplifier design methodology. Conventional AC-coupled neural amplifiers inherently reject input DC offset but have key limitations in area, linearity, DC drift, and...

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Veröffentlicht in:IEEE transactions on biomedical circuits and systems 2017-02, Vol.11 (1), p.161-176
Hauptverfasser: Bagheri, Arezu, Salam, Muhammad Tariqus, Perez Velazquez, Jose Luis, Genov, Roman
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creator Bagheri, Arezu
Salam, Muhammad Tariqus
Perez Velazquez, Jose Luis
Genov, Roman
description We review integrated circuits for low-frequency noise and offset rejection as a motivation for the presented digitally-assisted neural amplifier design methodology. Conventional AC-coupled neural amplifiers inherently reject input DC offset but have key limitations in area, linearity, DC drift, and spectral accuracy. Their chopper stabilization reduces low-frequency intrinsic noise at the cost of degraded area, input impedance and design complexity. DC-coupled implementations with digital high-pass filtering yield improved area, linearity, drift, and spectral accuracy and are inherently suitable for simple chopper stabilization. As a design example, a 56-channel 0.13 μm CMOS intracranial EEG interface is presented. DC offset of up to ±50 mV is rejected by a digital low-pass filter and a 16-bit delta-sigma DAC feeding back into the folding node of a folded-cascode LNA with CMRR of 65 dB. A bank of seven column-parallel fully differential SAR ADCs with ENOB of 6.6 are freely moving ratsshared among 56 channels resulting in 0.018 mm 2 effective channel area. Compensation-free direct input chopping yields integrated input-referred noise of 4.2 μV rms over the bandwidth of 1 Hz to 1 kHz. The 8.7 mm 2 chip dissipating 1.07 mW has been validated in vivo in online intracranial EEG monitoring in freely moving rats.
doi_str_mv 10.1109/TBCAS.2016.2539518
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Conventional AC-coupled neural amplifiers inherently reject input DC offset but have key limitations in area, linearity, DC drift, and spectral accuracy. Their chopper stabilization reduces low-frequency intrinsic noise at the cost of degraded area, input impedance and design complexity. DC-coupled implementations with digital high-pass filtering yield improved area, linearity, drift, and spectral accuracy and are inherently suitable for simple chopper stabilization. As a design example, a 56-channel 0.13 μm CMOS intracranial EEG interface is presented. DC offset of up to ±50 mV is rejected by a digital low-pass filter and a 16-bit delta-sigma DAC feeding back into the folding node of a folded-cascode LNA with CMRR of 65 dB. A bank of seven column-parallel fully differential SAR ADCs with ENOB of 6.6 are freely moving ratsshared among 56 channels resulting in 0.018 mm 2 effective channel area. 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subjects Amplifier design
Amplifiers
Amplifiers, Electronic
Animals
Bandwidths
Biomedical electronics
brain
Capacitors
Choppers (circuits)
Circuit design
closed-loop DC offset rejection
CMOS
Cutting
dc-coupled neural signal monitoring
Design
Digital to analog converters
Drift
EEG
Electric Impedance
Electrodes
Electroencephalography - instrumentation
epilepsy
Equipment Design
Impedance
implantable biomedical devices
in vivo
Input impedance
Integrated circuits
Linearity
Low pass filters
Low-frequency noise
microelectronic implant
mixed analog digital integrated circuits
Motivation
neural recording
Noise
Noise reduction
Rats
Rejection
Resistors
Signal Processing, Computer-Assisted
Stabilization
Transistors
title Low-Frequency Noise and Offset Rejection in DC-Coupled Neural Amplifiers: A Review and Digitally-Assisted Design Tutorial
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