An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and } Optimization
Graphics workloads make highly dynamic use of resources such as execution units (EUs), and thus can benefit from fast, fine-grain dynamic voltage and frequency scaling (DVFS) and retentive sleep. This paper presents a 14-nm graphics processing unit (GPU) prototype with modified EUs which include an...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2019-01, Vol.54 (1), p.144-157 |
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| creator | Meinerzhagen, Pascal A. Tokunaga, Carlos Malavasi, Andres Vaidya, Vaibhav Mendon, Ashwin Mathaikutty, D. Kulkarni, Jaydeep Augustine, Charles Cho, Minki Kim, Stephen T. Matthew, George E. Jain, Rinkle Ryan, Joseph Peng, Chung-Ching Paul, Somnath Vangal, Sriram Perez Esparza, Brando Cuellar, L. Woodman, M. Iyer, Bala Maiyuran, Subramaniam Chinya, G. Zou, Xiang Liao, Yuyun Ravichandran, Krishnan Wang, H. Khellah, Muhammad M. Tschanz, James W. De, Vivek |
| description | Graphics workloads make highly dynamic use of resources such as execution units (EUs), and thus can benefit from fast, fine-grain dynamic voltage and frequency scaling (DVFS) and retentive sleep. This paper presents a 14-nm graphics processing unit (GPU) prototype with modified EUs which include an integrated voltage regulator (IVR). The IVR enables energy-efficient EU turbo operation, data retention, and V_{\text {MIN}} optimization per EU. Silicon measurements show that IVR-enabled EU turbo operation offers up to 32% (average 29%) energy reduction at constant performance. |
| doi_str_mv | 10.1109/JSSC.2018.2875097 |
| format | Article |
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This paper presents a 14-nm graphics processing unit (GPU) prototype with modified EUs which include an integrated voltage regulator (IVR). The IVR enables energy-efficient EU turbo operation, data retention, and <inline-formula> <tex-math notation="LaTeX">V_{\text {MIN}} </tex-math></inline-formula> optimization per EU. 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This paper presents a 14-nm graphics processing unit (GPU) prototype with modified EUs which include an integrated voltage regulator (IVR). The IVR enables energy-efficient EU turbo operation, data retention, and <inline-formula> <tex-math notation="LaTeX">V_{\text {MIN}} </tex-math></inline-formula> optimization per EU. Silicon measurements show that IVR-enabled EU turbo operation offers up to 32% (average 29%) energy reduction at constant performance.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JSSC.2018.2875097</doi><tpages>14</tpages><orcidid>https://orcid.org/0000-0001-5207-1079</orcidid><orcidid>https://orcid.org/0000-0003-3745-122X</orcidid><orcidid>https://orcid.org/0000-0002-5444-5772</orcidid><orcidid>https://orcid.org/0000-0002-0258-6776</orcidid><orcidid>https://orcid.org/0000-0003-0317-4332</orcidid><orcidid>https://orcid.org/0000-0003-2271-4314</orcidid><orcidid>https://orcid.org/0000-0001-9908-669X</orcidid></addata></record> |
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| ispartof | IEEE journal of solid-state circuits, 2019-01, Vol.54 (1), p.144-157 |
| issn | 0018-9200 1558-173X |
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| subjects | <italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">V MIN optimization Clocks CMOS Dynamic scheduling Energy-efficient graphics processing unit (GPU) fine-grain dynamic voltage and frequency scaling (DVFS) Graphics boards Graphics processing units integrated voltage regulators (IVRs) Media Microprocessors Optimization Prototypes retentive sleep Sleep Voltage control Voltage regulators |
| title | An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and } Optimization |
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