Optimization of } Plateau for Deep-Oxide Trench SOI Lateral IGBT During Inductive Load Turn-OFF

Collector-emitter voltage ( {V}_{\textsf {CE}} ) plateau of the 500-V deep-oxide trench (DOT) silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) during inductive load turn-off is investigated and optimized for the first time in this paper, aiming to reduce the turn-off loss ( {E}_{ \mathrm{\scriptscriptstyle OFF}} ). The mechanism of {V}_{\textsf {CE}} plateau is revealed by TCAD simulation. In conventional DOT SOI-LIGBT, the large number of stored carries in the silicon region beneath the DOT (Region I) hinders the extension of depletion layer and slows down {V}_{\textsf {CE}} rising during turn-off, leading to a plateau phase. A novel DOT SOI-LIGBT with dual-controllable vertical field plates (CPFs) is proposed to shorten the {V}_{\textsf {CE}} plateau. The dual CPFs are arranged in the DOT and their electric potentials ( {V}_{\textsf {F} 1} and {V}_{\textsf {F} 2} ) are controlled through the connection with scrolled resistive polysilicon filed plate. By adjusting {V}_{\textsf {F} 1} and {V}_{\textsf {F} 2} , the accelerated depletion and extraction of stored carriers in Region I can be realized, resulting in a short {V}_{\mathbf {CE}} plateau duration. The {V}_{\mathbf {CE}} plateau duration can be decreased from 156 ns for the conventional SOI-LIGBT to 60 ns for the proposed SOI-LIGBT with {V}_{F1} = 0 V and {V}_{\textsf {F}2} = {0.5}\,\,{V}_{\textsf {CE}} . The proposed DOT SOI-LIGBT achieves an {E}_{ \mathrm{\scriptscriptstyle OFF}}