Power Supply- and Temperature-Aware I/O Buffer Model for Signal-Power Integrity Simulation
This paper presents the development and evaluation of a large-signal equivalent circuit model that accounts for the power supply fluctuation and temperature variation of I/O buffers circuit designed based on the fully depleted silicon on insulator (FDSOI) 28 nm process for signal-power integrity (SP...
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| Veröffentlicht in: | Mathematical problems in engineering 2018-01, Vol.2018 (2018), p.1-9 |
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| creator | Chaari, Abdelkader Zayer, Fakhreddine Souilem, Malek Dghais, Wael |
| description | This paper presents the development and evaluation of a large-signal equivalent circuit model that accounts for the power supply fluctuation and temperature variation of I/O buffers circuit designed based on the fully depleted silicon on insulator (FDSOI) 28 nm process for signal-power integrity (SPI) simulation. A solid electrical analysis based on the working mechanisms of the nominal I/O buffer information specification- (IBIS-) like model is presented to support the derivation of an accurate and computationally efficient behavioral model that captures the essential effects of the power supply bouncing under temperature variation. The formulation and extraction of the Lagrange interpolating polynomial are investigated to extend the nominal equivalent circuit model. The generated behavioral model is implemented using the Newton-Neville’s formula and validated in simultaneous switching output buffers (SSO) scenario under temperature variation. The numerical results show a good prediction accuracy of the time domain voltage and current waveforms as well as the eye diagram of the high-speed communication I/O link while speeding-up the transient simulation compared to the transistor level model. |
| doi_str_mv | 10.1155/2018/1356538 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_journals_2090630269</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>2090630269</sourcerecordid><originalsourceid>FETCH-LOGICAL-c360t-f35b1dbb0c430afd59a381ea7093d7e96dc67a1a8f800d309e0d66cb3fd1aa373</originalsourceid><addsrcrecordid>eNqF0M9LwzAUB_AgCs7pzbMUPGrcS7Ok7XEOfwyUCU4QL-WteZkdXVvTlrH_3owOPHrKI3zeD76MXQq4E0KpUQgiHgmptJLxERsIpSVXYhwd-xrCMReh_DxlZ02zBgiFEvGAfb1VW3LBe1fXxY4HWJpgQZuaHLadIz7ZoqNgNpoH9521Hr5WhorAVr4lX5VY8L5_Vra0cnm789-brsA2r8pzdmKxaOji8A7Zx-PDYvrMX-ZPs-nkhWdSQ8utVEthlkvIxhLQGpWgjAVhBIk0ESXaZDpCgbGNAYyEhMBonS2lNQJRRnLIrvu5tat-OmradF11zt_WpCEkoCWEOvHqtleZq5rGkU1rl2_Q7VIB6T69dJ9eekjP85uef-elwW3-n77qNXlDFv90CEr57b9DiXh_</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2090630269</pqid></control><display><type>article</type><title>Power Supply- and Temperature-Aware I/O Buffer Model for Signal-Power Integrity Simulation</title><source>Wiley Online Library Open Access</source><source>Elektronische Zeitschriftenbibliothek - Frei zugängliche E-Journals</source><source>Alma/SFX Local Collection</source><creator>Chaari, Abdelkader ; Zayer, Fakhreddine ; Souilem, Malek ; Dghais, Wael</creator><contributor>Lo Schiavo, Alessandro</contributor><creatorcontrib>Chaari, Abdelkader ; Zayer, Fakhreddine ; Souilem, Malek ; Dghais, Wael ; Lo Schiavo, Alessandro</creatorcontrib><description>This paper presents the development and evaluation of a large-signal equivalent circuit model that accounts for the power supply fluctuation and temperature variation of I/O buffers circuit designed based on the fully depleted silicon on insulator (FDSOI) 28 nm process for signal-power integrity (SPI) simulation. A solid electrical analysis based on the working mechanisms of the nominal I/O buffer information specification- (IBIS-) like model is presented to support the derivation of an accurate and computationally efficient behavioral model that captures the essential effects of the power supply bouncing under temperature variation. The formulation and extraction of the Lagrange interpolating polynomial are investigated to extend the nominal equivalent circuit model. The generated behavioral model is implemented using the Newton-Neville’s formula and validated in simultaneous switching output buffers (SSO) scenario under temperature variation. The numerical results show a good prediction accuracy of the time domain voltage and current waveforms as well as the eye diagram of the high-speed communication I/O link while speeding-up the transient simulation compared to the transistor level model.</description><identifier>ISSN: 1024-123X</identifier><identifier>EISSN: 1563-5147</identifier><identifier>DOI: 10.1155/2018/1356538</identifier><language>eng</language><publisher>Cairo, Egypt: Hindawi Publishing Corporation</publisher><subject>Automation ; Buffers ; Circuit design ; Communication ; Computer simulation ; Design ; Equivalent circuits ; Integrity ; Intellectual property ; Mathematical analysis ; Mathematical models ; Packaging ; Power supplies ; Power supply ; Semiconductors ; Signal processing ; Transistors ; Variation ; Waveforms</subject><ispartof>Mathematical problems in engineering, 2018-01, Vol.2018 (2018), p.1-9</ispartof><rights>Copyright © 2018 Wael Dghais et al.</rights><rights>Copyright © 2018 Wael Dghais et al. This is an open access article distributed under the Creative Commons Attribution License (the “License”), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Notwithstanding the ProQuest Terms and Conditions, you may use this content in accordance with the terms of the License. https://creativecommons.org/licenses/by/4.0</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c360t-f35b1dbb0c430afd59a381ea7093d7e96dc67a1a8f800d309e0d66cb3fd1aa373</citedby><cites>FETCH-LOGICAL-c360t-f35b1dbb0c430afd59a381ea7093d7e96dc67a1a8f800d309e0d66cb3fd1aa373</cites><orcidid>0000-0002-1777-2213 ; 0000-0002-0002-8965 ; 0000-0003-1989-5951</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,776,780,27901,27902</link.rule.ids></links><search><contributor>Lo Schiavo, Alessandro</contributor><creatorcontrib>Chaari, Abdelkader</creatorcontrib><creatorcontrib>Zayer, Fakhreddine</creatorcontrib><creatorcontrib>Souilem, Malek</creatorcontrib><creatorcontrib>Dghais, Wael</creatorcontrib><title>Power Supply- and Temperature-Aware I/O Buffer Model for Signal-Power Integrity Simulation</title><title>Mathematical problems in engineering</title><description>This paper presents the development and evaluation of a large-signal equivalent circuit model that accounts for the power supply fluctuation and temperature variation of I/O buffers circuit designed based on the fully depleted silicon on insulator (FDSOI) 28 nm process for signal-power integrity (SPI) simulation. A solid electrical analysis based on the working mechanisms of the nominal I/O buffer information specification- (IBIS-) like model is presented to support the derivation of an accurate and computationally efficient behavioral model that captures the essential effects of the power supply bouncing under temperature variation. The formulation and extraction of the Lagrange interpolating polynomial are investigated to extend the nominal equivalent circuit model. The generated behavioral model is implemented using the Newton-Neville’s formula and validated in simultaneous switching output buffers (SSO) scenario under temperature variation. The numerical results show a good prediction accuracy of the time domain voltage and current waveforms as well as the eye diagram of the high-speed communication I/O link while speeding-up the transient simulation compared to the transistor level model.</description><subject>Automation</subject><subject>Buffers</subject><subject>Circuit design</subject><subject>Communication</subject><subject>Computer simulation</subject><subject>Design</subject><subject>Equivalent circuits</subject><subject>Integrity</subject><subject>Intellectual property</subject><subject>Mathematical analysis</subject><subject>Mathematical models</subject><subject>Packaging</subject><subject>Power supplies</subject><subject>Power supply</subject><subject>Semiconductors</subject><subject>Signal processing</subject><subject>Transistors</subject><subject>Variation</subject><subject>Waveforms</subject><issn>1024-123X</issn><issn>1563-5147</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2018</creationdate><recordtype>article</recordtype><sourceid>RHX</sourceid><sourceid>BENPR</sourceid><recordid>eNqF0M9LwzAUB_AgCs7pzbMUPGrcS7Ok7XEOfwyUCU4QL-WteZkdXVvTlrH_3owOPHrKI3zeD76MXQq4E0KpUQgiHgmptJLxERsIpSVXYhwd-xrCMReh_DxlZ02zBgiFEvGAfb1VW3LBe1fXxY4HWJpgQZuaHLadIz7ZoqNgNpoH9521Hr5WhorAVr4lX5VY8L5_Vra0cnm789-brsA2r8pzdmKxaOji8A7Zx-PDYvrMX-ZPs-nkhWdSQ8utVEthlkvIxhLQGpWgjAVhBIk0ESXaZDpCgbGNAYyEhMBonS2lNQJRRnLIrvu5tat-OmradF11zt_WpCEkoCWEOvHqtleZq5rGkU1rl2_Q7VIB6T69dJ9eekjP85uef-elwW3-n77qNXlDFv90CEr57b9DiXh_</recordid><startdate>20180101</startdate><enddate>20180101</enddate><creator>Chaari, Abdelkader</creator><creator>Zayer, Fakhreddine</creator><creator>Souilem, Malek</creator><creator>Dghais, Wael</creator><general>Hindawi Publishing Corporation</general><general>Hindawi</general><general>Hindawi Limited</general><scope>ADJCN</scope><scope>AHFXO</scope><scope>RHU</scope><scope>RHW</scope><scope>RHX</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7TB</scope><scope>8FD</scope><scope>8FE</scope><scope>8FG</scope><scope>ABJCF</scope><scope>ABUWG</scope><scope>AFKRA</scope><scope>ARAPS</scope><scope>AZQEC</scope><scope>BENPR</scope><scope>BGLVJ</scope><scope>CCPQU</scope><scope>CWDGH</scope><scope>DWQXO</scope><scope>FR3</scope><scope>GNUQQ</scope><scope>HCIFZ</scope><scope>JQ2</scope><scope>K7-</scope><scope>KR7</scope><scope>L6V</scope><scope>M7S</scope><scope>P5Z</scope><scope>P62</scope><scope>PIMPY</scope><scope>PQEST</scope><scope>PQQKQ</scope><scope>PQUKI</scope><scope>PRINS</scope><scope>PTHSS</scope><orcidid>https://orcid.org/0000-0002-1777-2213</orcidid><orcidid>https://orcid.org/0000-0002-0002-8965</orcidid><orcidid>https://orcid.org/0000-0003-1989-5951</orcidid></search><sort><creationdate>20180101</creationdate><title>Power Supply- and Temperature-Aware I/O Buffer Model for Signal-Power Integrity Simulation</title><author>Chaari, Abdelkader ; Zayer, Fakhreddine ; Souilem, Malek ; Dghais, Wael</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c360t-f35b1dbb0c430afd59a381ea7093d7e96dc67a1a8f800d309e0d66cb3fd1aa373</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2018</creationdate><topic>Automation</topic><topic>Buffers</topic><topic>Circuit design</topic><topic>Communication</topic><topic>Computer simulation</topic><topic>Design</topic><topic>Equivalent circuits</topic><topic>Integrity</topic><topic>Intellectual property</topic><topic>Mathematical analysis</topic><topic>Mathematical models</topic><topic>Packaging</topic><topic>Power supplies</topic><topic>Power supply</topic><topic>Semiconductors</topic><topic>Signal processing</topic><topic>Transistors</topic><topic>Variation</topic><topic>Waveforms</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Chaari, Abdelkader</creatorcontrib><creatorcontrib>Zayer, Fakhreddine</creatorcontrib><creatorcontrib>Souilem, Malek</creatorcontrib><creatorcontrib>Dghais, Wael</creatorcontrib><collection>الدوريات العلمية والإحصائية - e-Marefa Academic and Statistical Periodicals</collection><collection>معرفة - المحتوى العربي الأكاديمي المتكامل - e-Marefa Academic Complete</collection><collection>Hindawi Publishing Complete</collection><collection>Hindawi Publishing Subscription Journals</collection><collection>Hindawi Publishing Open Access</collection><collection>CrossRef</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest SciTech Collection</collection><collection>ProQuest Technology Collection</collection><collection>Materials Science & Engineering Collection</collection><collection>ProQuest Central (Alumni Edition)</collection><collection>ProQuest Central UK/Ireland</collection><collection>Advanced Technologies & Aerospace Collection</collection><collection>ProQuest Central Essentials</collection><collection>ProQuest Central</collection><collection>Technology Collection</collection><collection>ProQuest One Community College</collection><collection>Middle East & Africa Database</collection><collection>ProQuest Central Korea</collection><collection>Engineering Research Database</collection><collection>ProQuest Central Student</collection><collection>SciTech Premium Collection</collection><collection>ProQuest Computer Science Collection</collection><collection>Computer Science Database</collection><collection>Civil Engineering Abstracts</collection><collection>ProQuest Engineering Collection</collection><collection>Engineering Database</collection><collection>Advanced Technologies & Aerospace Database</collection><collection>ProQuest Advanced Technologies & Aerospace Collection</collection><collection>Publicly Available Content Database</collection><collection>ProQuest One Academic Eastern Edition (DO NOT USE)</collection><collection>ProQuest One Academic</collection><collection>ProQuest One Academic UKI Edition</collection><collection>ProQuest Central China</collection><collection>Engineering Collection</collection><jtitle>Mathematical problems in engineering</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Chaari, Abdelkader</au><au>Zayer, Fakhreddine</au><au>Souilem, Malek</au><au>Dghais, Wael</au><au>Lo Schiavo, Alessandro</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Power Supply- and Temperature-Aware I/O Buffer Model for Signal-Power Integrity Simulation</atitle><jtitle>Mathematical problems in engineering</jtitle><date>2018-01-01</date><risdate>2018</risdate><volume>2018</volume><issue>2018</issue><spage>1</spage><epage>9</epage><pages>1-9</pages><issn>1024-123X</issn><eissn>1563-5147</eissn><abstract>This paper presents the development and evaluation of a large-signal equivalent circuit model that accounts for the power supply fluctuation and temperature variation of I/O buffers circuit designed based on the fully depleted silicon on insulator (FDSOI) 28 nm process for signal-power integrity (SPI) simulation. A solid electrical analysis based on the working mechanisms of the nominal I/O buffer information specification- (IBIS-) like model is presented to support the derivation of an accurate and computationally efficient behavioral model that captures the essential effects of the power supply bouncing under temperature variation. The formulation and extraction of the Lagrange interpolating polynomial are investigated to extend the nominal equivalent circuit model. The generated behavioral model is implemented using the Newton-Neville’s formula and validated in simultaneous switching output buffers (SSO) scenario under temperature variation. The numerical results show a good prediction accuracy of the time domain voltage and current waveforms as well as the eye diagram of the high-speed communication I/O link while speeding-up the transient simulation compared to the transistor level model.</abstract><cop>Cairo, Egypt</cop><pub>Hindawi Publishing Corporation</pub><doi>10.1155/2018/1356538</doi><tpages>9</tpages><orcidid>https://orcid.org/0000-0002-1777-2213</orcidid><orcidid>https://orcid.org/0000-0002-0002-8965</orcidid><orcidid>https://orcid.org/0000-0003-1989-5951</orcidid><oa>free_for_read</oa></addata></record> |
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| subjects | Automation Buffers Circuit design Communication Computer simulation Design Equivalent circuits Integrity Intellectual property Mathematical analysis Mathematical models Packaging Power supplies Power supply Semiconductors Signal processing Transistors Variation Waveforms |
| title | Power Supply- and Temperature-Aware I/O Buffer Model for Signal-Power Integrity Simulation |
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