Dual-gate MoS2 transistors with sub-10 nm top-gate high-k dielectrics
High quality sub-10 nm high-k dielectrics are deposited on top of MoS2 and evaluated using a dual-gate field effect transistor configuration. Comparison between top-gate HfO2 and an Al2O3/HfO2 bilayer shows significant improvement in device performance due to the insertion of the thin Al2O3 layer. T...
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Veröffentlicht in: | Applied physics letters 2018-06, Vol.112 (25) |
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creator | Bolshakov, Pavel Khosravi, Ava Zhao, Peng Hurley, Paul K. Hinkle, Christopher L. Wallace, Robert M. Young, Chadwin D. |
description | High quality sub-10 nm high-k dielectrics are deposited on top of MoS2 and evaluated using a dual-gate field effect transistor configuration. Comparison between top-gate HfO2 and an Al2O3/HfO2 bilayer shows significant improvement in device performance due to the insertion of the thin Al2O3 layer. The results show that the Al2O3 buffer layer improves the interface quality by effectively reducing the net fixed positive oxide charge at the top-gate MoS2/high-k dielectric interface. Dual-gate sweeping, where both the top-gate and the back-gate are swept simultaneously, provides significant insight into the role of these oxide charges and improves overall device performance. Dual-gate transistors encapsulated in an Al2O3 dielectric demonstrate a near-ideal subthreshold swing of ∼60 mV/dec and a high field effect mobility of 100 cm2/V·s. |
doi_str_mv | 10.1063/1.5027102 |
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Comparison between top-gate HfO2 and an Al2O3/HfO2 bilayer shows significant improvement in device performance due to the insertion of the thin Al2O3 layer. The results show that the Al2O3 buffer layer improves the interface quality by effectively reducing the net fixed positive oxide charge at the top-gate MoS2/high-k dielectric interface. Dual-gate sweeping, where both the top-gate and the back-gate are swept simultaneously, provides significant insight into the role of these oxide charges and improves overall device performance. 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Comparison between top-gate HfO2 and an Al2O3/HfO2 bilayer shows significant improvement in device performance due to the insertion of the thin Al2O3 layer. The results show that the Al2O3 buffer layer improves the interface quality by effectively reducing the net fixed positive oxide charge at the top-gate MoS2/high-k dielectric interface. Dual-gate sweeping, where both the top-gate and the back-gate are swept simultaneously, provides significant insight into the role of these oxide charges and improves overall device performance. Dual-gate transistors encapsulated in an Al2O3 dielectric demonstrate a near-ideal subthreshold swing of ∼60 mV/dec and a high field effect mobility of 100 cm2/V·s.</description><subject>Aluminum oxide</subject><subject>Applied physics</subject><subject>Buffer layers</subject><subject>Dielectrics</subject><subject>Field effect transistors</subject><subject>Hafnium oxide</subject><subject>Molybdenum disulfide</subject><subject>Semiconductor devices</subject><subject>Transistors</subject><issn>0003-6951</issn><issn>1077-3118</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2018</creationdate><recordtype>article</recordtype><recordid>eNp90MtKAzEUBuAgCtbqwjcYcKWQenKZ21KqVqHiQl2HTJK2qe1kTDKKO7e-pk_i6BRdCK4OBz7-c0HokMCIQMZOySgFmhOgW2hAIM8xI6TYRgMAYDgrU7KL9kJYdm1KGRugyXkrV3guo0lu3B1Nopd1sCE6H5IXGxdJaCtM4OPtvV4n0TU9Xdj5Aj8m2pqVUdFbFfbRzkyugjnY1CF6uLy4H1_h6e3kenw2xYrmOcV6xkAz3Q1XwEqmNSiZVpzzihcslxXPyswYXhhZaKIZ58BSTlh3kko5IyUboqM-t_HuqTUhiqVrfd2NFBSKgkFJv9Vxr5R3IXgzE423a-lfBQHx9SdBxOZPnT3pbVA2ymhd_YOfnf-FoumW_wf_Tf4EU-d0Ew</recordid><startdate>20180618</startdate><enddate>20180618</enddate><creator>Bolshakov, Pavel</creator><creator>Khosravi, Ava</creator><creator>Zhao, Peng</creator><creator>Hurley, Paul K.</creator><creator>Hinkle, Christopher L.</creator><creator>Wallace, Robert M.</creator><creator>Young, Chadwin D.</creator><general>American Institute of Physics</general><scope>AAYXX</scope><scope>CITATION</scope><scope>8FD</scope><scope>H8D</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-6098-6823</orcidid><orcidid>https://orcid.org/0000-0001-5566-4806</orcidid><orcidid>https://orcid.org/0000-0002-3530-6400</orcidid><orcidid>https://orcid.org/0000-0003-0690-7423</orcidid></search><sort><creationdate>20180618</creationdate><title>Dual-gate MoS2 transistors with sub-10 nm top-gate high-k dielectrics</title><author>Bolshakov, Pavel ; Khosravi, Ava ; Zhao, Peng ; Hurley, Paul K. ; Hinkle, Christopher L. ; Wallace, Robert M. ; Young, Chadwin D.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c2772-df30d3d052c0393dd0ca5b444b4837ab4696ee48ea8d1d344035413027c543193</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2018</creationdate><topic>Aluminum oxide</topic><topic>Applied physics</topic><topic>Buffer layers</topic><topic>Dielectrics</topic><topic>Field effect transistors</topic><topic>Hafnium oxide</topic><topic>Molybdenum disulfide</topic><topic>Semiconductor devices</topic><topic>Transistors</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Bolshakov, Pavel</creatorcontrib><creatorcontrib>Khosravi, Ava</creatorcontrib><creatorcontrib>Zhao, Peng</creatorcontrib><creatorcontrib>Hurley, Paul K.</creatorcontrib><creatorcontrib>Hinkle, Christopher L.</creatorcontrib><creatorcontrib>Wallace, Robert M.</creatorcontrib><creatorcontrib>Young, Chadwin D.</creatorcontrib><collection>CrossRef</collection><collection>Technology Research Database</collection><collection>Aerospace Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Applied physics letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Bolshakov, Pavel</au><au>Khosravi, Ava</au><au>Zhao, Peng</au><au>Hurley, Paul K.</au><au>Hinkle, Christopher L.</au><au>Wallace, Robert M.</au><au>Young, Chadwin D.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Dual-gate MoS2 transistors with sub-10 nm top-gate high-k dielectrics</atitle><jtitle>Applied physics letters</jtitle><date>2018-06-18</date><risdate>2018</risdate><volume>112</volume><issue>25</issue><issn>0003-6951</issn><eissn>1077-3118</eissn><coden>APPLAB</coden><abstract>High quality sub-10 nm high-k dielectrics are deposited on top of MoS2 and evaluated using a dual-gate field effect transistor configuration. Comparison between top-gate HfO2 and an Al2O3/HfO2 bilayer shows significant improvement in device performance due to the insertion of the thin Al2O3 layer. The results show that the Al2O3 buffer layer improves the interface quality by effectively reducing the net fixed positive oxide charge at the top-gate MoS2/high-k dielectric interface. Dual-gate sweeping, where both the top-gate and the back-gate are swept simultaneously, provides significant insight into the role of these oxide charges and improves overall device performance. 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source | AIP Journals Complete; Alma/SFX Local Collection |
subjects | Aluminum oxide Applied physics Buffer layers Dielectrics Field effect transistors Hafnium oxide Molybdenum disulfide Semiconductor devices Transistors |
title | Dual-gate MoS2 transistors with sub-10 nm top-gate high-k dielectrics |
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