Distributed Modeling of Layout Parasitics in Large-Area High-Speed Silicon Power Devices
This paper reports a technique for generating a lumped-element distributed model for silicon power devices that takes into account the effect of layout parasitics. The proposed methodology exploits the high-frequency modeling approach of microstrips and striplines to describe both the passive parts...
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| Veröffentlicht in: | IEEE transactions on power electronics 2007-09, Vol.22 (5), p.1847-1856 |
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| container_title | IEEE transactions on power electronics |
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| creator | Biondi, T. Greco, G. Allia, M.C. Liotta, S.F. Bazzano, G. Rinaudo, S. |
| description | This paper reports a technique for generating a lumped-element distributed model for silicon power devices that takes into account the effect of layout parasitics. The proposed methodology exploits the high-frequency modeling approach of microstrips and striplines to describe both the passive parts of the device and elementary transistor cells. A semi-empirical model for the elementary transistor cells of the power device is also proposed. Parameter extraction is described and validated by direct comparison with device simulations of an actual device. The proposed modeling approach is employed to investigate the internal current distribution of a high-voltage silicon power MOSFET supplied by STMicroelectronics during the turnoff transient. The tradeoff that must be accomplished between accuracy and complexity is discussed. The effect of increased switching frequency on the device current distribution is also reported explaining how it may lead to performance degradation and device failure. |
| doi_str_mv | 10.1109/TPEL.2007.904241 |
| format | Article |
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The proposed methodology exploits the high-frequency modeling approach of microstrips and striplines to describe both the passive parts of the device and elementary transistor cells. A semi-empirical model for the elementary transistor cells of the power device is also proposed. Parameter extraction is described and validated by direct comparison with device simulations of an actual device. The proposed modeling approach is employed to investigate the internal current distribution of a high-voltage silicon power MOSFET supplied by STMicroelectronics during the turnoff transient. The tradeoff that must be accomplished between accuracy and complexity is discussed. The effect of increased switching frequency on the device current distribution is also reported explaining how it may lead to performance degradation and device failure.</description><identifier>ISSN: 0885-8993</identifier><identifier>EISSN: 1941-0107</identifier><identifier>DOI: 10.1109/TPEL.2007.904241</identifier><identifier>CODEN: ITPEE8</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Current distribution ; Devices ; Distributed control ; Distributed modeling ; Distributed power generation ; Electric currents ; Electrical engineering ; Electrical engineering. Electrical power engineering ; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics ; Electronics ; Exact sciences and technology ; Failure ; Frequencies ; high-speed ; layout parasitics ; Mathematical models ; Microstrip components ; MOSFET circuits ; Other multijunction devices. Power transistors. Thyristors ; Parameter extraction ; power devices ; Power electronics, power supplies ; Power generation ; Power MOSFET ; Semiconductor devices ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Silicon ; silicon technology ; Stripline ; Transistors</subject><ispartof>IEEE transactions on power electronics, 2007-09, Vol.22 (5), p.1847-1856</ispartof><rights>2007 INIST-CNRS</rights><rights>Copyright Institute of Electrical and Electronics Engineers, Inc. (IEEE) Sep 2007</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c415t-bd6d988cbbed87ce599f54d47c3aedcd1cbd6e4a4200b4832b594fca71e881363</citedby><cites>FETCH-LOGICAL-c415t-bd6d988cbbed87ce599f54d47c3aedcd1cbd6e4a4200b4832b594fca71e881363</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4300858$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27922,27923,54756</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4300858$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=19087966$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Biondi, T.</creatorcontrib><creatorcontrib>Greco, G.</creatorcontrib><creatorcontrib>Allia, M.C.</creatorcontrib><creatorcontrib>Liotta, S.F.</creatorcontrib><creatorcontrib>Bazzano, G.</creatorcontrib><creatorcontrib>Rinaudo, S.</creatorcontrib><title>Distributed Modeling of Layout Parasitics in Large-Area High-Speed Silicon Power Devices</title><title>IEEE transactions on power electronics</title><addtitle>TPEL</addtitle><description>This paper reports a technique for generating a lumped-element distributed model for silicon power devices that takes into account the effect of layout parasitics. The proposed methodology exploits the high-frequency modeling approach of microstrips and striplines to describe both the passive parts of the device and elementary transistor cells. A semi-empirical model for the elementary transistor cells of the power device is also proposed. Parameter extraction is described and validated by direct comparison with device simulations of an actual device. The proposed modeling approach is employed to investigate the internal current distribution of a high-voltage silicon power MOSFET supplied by STMicroelectronics during the turnoff transient. The tradeoff that must be accomplished between accuracy and complexity is discussed. The effect of increased switching frequency on the device current distribution is also reported explaining how it may lead to performance degradation and device failure.</description><subject>Applied sciences</subject><subject>Current distribution</subject><subject>Devices</subject><subject>Distributed control</subject><subject>Distributed modeling</subject><subject>Distributed power generation</subject><subject>Electric currents</subject><subject>Electrical engineering</subject><subject>Electrical engineering. Electrical power engineering</subject><subject>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Failure</subject><subject>Frequencies</subject><subject>high-speed</subject><subject>layout parasitics</subject><subject>Mathematical models</subject><subject>Microstrip components</subject><subject>MOSFET circuits</subject><subject>Other multijunction devices. Power transistors. Thyristors</subject><subject>Parameter extraction</subject><subject>power devices</subject><subject>Power electronics, power supplies</subject><subject>Power generation</subject><subject>Power MOSFET</subject><subject>Semiconductor devices</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Silicon</subject><subject>silicon technology</subject><subject>Stripline</subject><subject>Transistors</subject><issn>0885-8993</issn><issn>1941-0107</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2007</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqFkcFLHDEUxkNR6Gp7L_QyCNrTbN-bZGaSo6xaCytd0EJvIZN5s0bGyZrMKP73Zlmp0EM9BV5-3wcfP8a-IMwRQX2_WZ0v5wVAPVcgCoEf2AyVwBwQ6j02AynLXCrFP7KDGO8AUJSAM_bnzMUxuGYaqc2ufEu9G9aZ77KlefbTmK1MMNGNzsbMDekY1pSfBjLZpVvf5tcbSrFr1zvrh2zlnyhkZ_ToLMVPbL8zfaTPr-8h-31xfrO4zJe_fvxcnC5zK7Ac86atWiWlbRpqZW2pVKorRStqyw21tkWbCBJGpGmNkLxoSiU6a2okKZFX_JB92_Vugn-YKI763kVLfW8G8lPUCniFUqboe6SUUFWFqDGRJ_8luRCgKl4k8Ogf8M5PYUh7dZHKVMGxThDsIBt8jIE6vQnu3oRnjaC37vTWnd660zt3KXL82muiNX0XzGBdfMspkLWqtuO_7jhHRH-_BQeQpeQvTyOhGw</recordid><startdate>20070901</startdate><enddate>20070901</enddate><creator>Biondi, T.</creator><creator>Greco, G.</creator><creator>Allia, M.C.</creator><creator>Liotta, S.F.</creator><creator>Bazzano, G.</creator><creator>Rinaudo, S.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Electrical power engineering</topic><topic>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Failure</topic><topic>Frequencies</topic><topic>high-speed</topic><topic>layout parasitics</topic><topic>Mathematical models</topic><topic>Microstrip components</topic><topic>MOSFET circuits</topic><topic>Other multijunction devices. Power transistors. Thyristors</topic><topic>Parameter extraction</topic><topic>power devices</topic><topic>Power electronics, power supplies</topic><topic>Power generation</topic><topic>Power MOSFET</topic><topic>Semiconductor devices</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Silicon</topic><topic>silicon technology</topic><topic>Stripline</topic><topic>Transistors</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Biondi, T.</creatorcontrib><creatorcontrib>Greco, G.</creatorcontrib><creatorcontrib>Allia, M.C.</creatorcontrib><creatorcontrib>Liotta, S.F.</creatorcontrib><creatorcontrib>Bazzano, G.</creatorcontrib><creatorcontrib>Rinaudo, S.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><collection>Technology Research Database</collection><collection>Engineering Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Civil Engineering Abstracts</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><jtitle>IEEE transactions on power electronics</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Biondi, T.</au><au>Greco, G.</au><au>Allia, M.C.</au><au>Liotta, S.F.</au><au>Bazzano, G.</au><au>Rinaudo, S.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Distributed Modeling of Layout Parasitics in Large-Area High-Speed Silicon Power Devices</atitle><jtitle>IEEE transactions on power electronics</jtitle><stitle>TPEL</stitle><date>2007-09-01</date><risdate>2007</risdate><volume>22</volume><issue>5</issue><spage>1847</spage><epage>1856</epage><pages>1847-1856</pages><issn>0885-8993</issn><eissn>1941-0107</eissn><coden>ITPEE8</coden><abstract>This paper reports a technique for generating a lumped-element distributed model for silicon power devices that takes into account the effect of layout parasitics. The proposed methodology exploits the high-frequency modeling approach of microstrips and striplines to describe both the passive parts of the device and elementary transistor cells. A semi-empirical model for the elementary transistor cells of the power device is also proposed. Parameter extraction is described and validated by direct comparison with device simulations of an actual device. The proposed modeling approach is employed to investigate the internal current distribution of a high-voltage silicon power MOSFET supplied by STMicroelectronics during the turnoff transient. The tradeoff that must be accomplished between accuracy and complexity is discussed. The effect of increased switching frequency on the device current distribution is also reported explaining how it may lead to performance degradation and device failure.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TPEL.2007.904241</doi><tpages>10</tpages></addata></record> |
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| identifier | ISSN: 0885-8993 |
| ispartof | IEEE transactions on power electronics, 2007-09, Vol.22 (5), p.1847-1856 |
| issn | 0885-8993 1941-0107 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Current distribution Devices Distributed control Distributed modeling Distributed power generation Electric currents Electrical engineering Electrical engineering. Electrical power engineering Electronic equipment and fabrication. Passive components, printed wiring boards, connectics Electronics Exact sciences and technology Failure Frequencies high-speed layout parasitics Mathematical models Microstrip components MOSFET circuits Other multijunction devices. Power transistors. Thyristors Parameter extraction power devices Power electronics, power supplies Power generation Power MOSFET Semiconductor devices Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon silicon technology Stripline Transistors |
| title | Distributed Modeling of Layout Parasitics in Large-Area High-Speed Silicon Power Devices |
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