FPGA implementation of an optimized key expansion module of AES algorithm for secure transmission of personal ECG signals

Advanced Encryption Standard was published as Federal Information Processing Standard by National Institute of Standards and Technology in 2001. AES is a symmetric non fiestel block cipher cryptographic algorithm that encrypts and decrypts the data block of 128 bits using different key sizes (128, 192, 256). Based on the block sizes, the number of rounds of encryption and decryption operations and the number of subkeys generated from the main key differs. In this proposed algorithm, the subkey generation architecture is altered to speed up the process of generating the subkeys from the main key. The proposed architecture is simulated and is implemented in FPGA Virtex 5 XC5VLX50T and it is found that the proposed architecture generates all the subkeys by saving 50% of the time taken by architecture proposed in 2001. This paper discusses the implementation of the new proposed algorithm for encryption and decryption process of ECG signals for the purpose of secure communication.