A Space Vector Modulation Scheme of the Quasi-Z-Source Three-Level T-Type Inverter for Common-Mode Voltage Reduction
The conventional three-level inverter suffers the limitation of voltage buck operation. In order to give both voltage buck and boost operation capability, the quasi-Z-source three-level T-type inverter (3LT 2 I) has been proposed. This paper further proposes a space vector modulation (SVM) scheme fo...
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| Veröffentlicht in: | IEEE transactions on industrial electronics (1982) 2018-10, Vol.65 (10), p.8340-8350 |
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| container_title | IEEE transactions on industrial electronics (1982) |
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| creator | Qin, Changwei Zhang, Chenghui Chen, Alian Xing, Xiangyang Zhang, Guangxian |
| description | The conventional three-level inverter suffers the limitation of voltage buck operation. In order to give both voltage buck and boost operation capability, the quasi-Z-source three-level T-type inverter (3LT 2 I) has been proposed. This paper further proposes a space vector modulation (SVM) scheme for the quasi-Z-source 3LT 2 I to reduce the magnitude and slew rate of common-mode voltage (CMV). By properly selecting the shoot-through phase, the shoot-through states are inserted within zero vector in order not to affect the active states and output voltage. Doing so, the CMV generated by the quasi-Z-source 3LT 2 I is restricted within one-sixth of dc-link voltage, and voltage boosting and CMV reduction can be simultaneously realized. In addition, high dc-link voltage utilization can be maintained. The proposed scheme has been verified in both simulations and experiments. Comparisons are conducted with the conventional SVM method and the phase-shifted sinusoidal PWM method. |
| doi_str_mv | 10.1109/TIE.2018.2798611 |
| format | Article |
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In order to give both voltage buck and boost operation capability, the quasi-Z-source three-level T-type inverter (3LT 2 I) has been proposed. This paper further proposes a space vector modulation (SVM) scheme for the quasi-Z-source 3LT 2 I to reduce the magnitude and slew rate of common-mode voltage (CMV). By properly selecting the shoot-through phase, the shoot-through states are inserted within zero vector in order not to affect the active states and output voltage. Doing so, the CMV generated by the quasi-Z-source 3LT 2 I is restricted within one-sixth of dc-link voltage, and voltage boosting and CMV reduction can be simultaneously realized. In addition, high dc-link voltage utilization can be maintained. The proposed scheme has been verified in both simulations and experiments. Comparisons are conducted with the conventional SVM method and the phase-shifted sinusoidal PWM method.</description><identifier>ISSN: 0278-0046</identifier><identifier>EISSN: 1557-9948</identifier><identifier>DOI: 10.1109/TIE.2018.2798611</identifier><identifier>CODEN: ITIED6</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Boosting ; Common-mode voltage (CMV) reduction ; Electric potential ; Inverters ; Modulation ; Network topology ; quasi-Z-source ; Slew rate ; Space vector modulation ; Support vector machines ; Switches ; three-level T-type inverter (3LT<inline-formula xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> <tex-math notation="LaTeX"> ^2</tex-math> </inline-formula>I) ; Topology ; voltage boosting ; Voltage reduction</subject><ispartof>IEEE transactions on industrial electronics (1982), 2018-10, Vol.65 (10), p.8340-8350</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2018</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c291t-a76e045ea9c76a3cfd34a81853d1619255cd5837a40496474f90523368e32a23</citedby><cites>FETCH-LOGICAL-c291t-a76e045ea9c76a3cfd34a81853d1619255cd5837a40496474f90523368e32a23</cites><orcidid>0000-0002-4467-0677 ; 0000-0001-7078-7783 ; 0000-0003-4919-4662</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8270653$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27923,27924,54757</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8270653$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Qin, Changwei</creatorcontrib><creatorcontrib>Zhang, Chenghui</creatorcontrib><creatorcontrib>Chen, Alian</creatorcontrib><creatorcontrib>Xing, Xiangyang</creatorcontrib><creatorcontrib>Zhang, Guangxian</creatorcontrib><title>A Space Vector Modulation Scheme of the Quasi-Z-Source Three-Level T-Type Inverter for Common-Mode Voltage Reduction</title><title>IEEE transactions on industrial electronics (1982)</title><addtitle>TIE</addtitle><description>The conventional three-level inverter suffers the limitation of voltage buck operation. In order to give both voltage buck and boost operation capability, the quasi-Z-source three-level T-type inverter (3LT 2 I) has been proposed. This paper further proposes a space vector modulation (SVM) scheme for the quasi-Z-source 3LT 2 I to reduce the magnitude and slew rate of common-mode voltage (CMV). By properly selecting the shoot-through phase, the shoot-through states are inserted within zero vector in order not to affect the active states and output voltage. Doing so, the CMV generated by the quasi-Z-source 3LT 2 I is restricted within one-sixth of dc-link voltage, and voltage boosting and CMV reduction can be simultaneously realized. In addition, high dc-link voltage utilization can be maintained. The proposed scheme has been verified in both simulations and experiments. Comparisons are conducted with the conventional SVM method and the phase-shifted sinusoidal PWM method.</description><subject>Boosting</subject><subject>Common-mode voltage (CMV) reduction</subject><subject>Electric potential</subject><subject>Inverters</subject><subject>Modulation</subject><subject>Network topology</subject><subject>quasi-Z-source</subject><subject>Slew rate</subject><subject>Space vector modulation</subject><subject>Support vector machines</subject><subject>Switches</subject><subject>three-level T-type inverter (3LT<inline-formula xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> <tex-math notation="LaTeX"> ^2</tex-math> </inline-formula>I)</subject><subject>Topology</subject><subject>voltage boosting</subject><subject>Voltage reduction</subject><issn>0278-0046</issn><issn>1557-9948</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2018</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kE1LAzEQQIMoWKt3wUvAc-rkazc5llK1UBHt4sHLErKzdkvb1Oxuof_elBZPc3nzZniE3HMYcQ72qZhNRwK4GYncmozzCzLgWufMWmUuyQBEbhiAyq7JTduuALjSXA9IN6aLnfNIv9B3IdK3UPVr1zVhSxd-iRukoabdEulH79qGfbNF6GPCi2VEZHPc45oWrDjskM62e4wdRlonzyRsNmHLki6pw7pzP0g_ser9UX1Lrmq3bvHuPIekeJ4Wk1c2f3-ZTcZz5oXlHXN5hqA0OuvzzElfV1I5w42WFc-4FVr7ShuZOwXKZipXtQUtpMwMSuGEHJLHk3YXw2-PbVeu0vPbdLEUoAG0tcIkCk6Uj6FtI9blLjYbFw8lh_KYtkxpy2Pa8pw2rTycVhpE_MeNyCHTUv4B6KdzKQ</recordid><startdate>20181001</startdate><enddate>20181001</enddate><creator>Qin, Changwei</creator><creator>Zhang, Chenghui</creator><creator>Chen, Alian</creator><creator>Xing, Xiangyang</creator><creator>Zhang, Guangxian</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-4467-0677</orcidid><orcidid>https://orcid.org/0000-0001-7078-7783</orcidid><orcidid>https://orcid.org/0000-0003-4919-4662</orcidid></search><sort><creationdate>20181001</creationdate><title>A Space Vector Modulation Scheme of the Quasi-Z-Source Three-Level T-Type Inverter for Common-Mode Voltage Reduction</title><author>Qin, Changwei ; Zhang, Chenghui ; Chen, Alian ; Xing, Xiangyang ; Zhang, Guangxian</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c291t-a76e045ea9c76a3cfd34a81853d1619255cd5837a40496474f90523368e32a23</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2018</creationdate><topic>Boosting</topic><topic>Common-mode voltage (CMV) reduction</topic><topic>Electric potential</topic><topic>Inverters</topic><topic>Modulation</topic><topic>Network topology</topic><topic>quasi-Z-source</topic><topic>Slew rate</topic><topic>Space vector modulation</topic><topic>Support vector machines</topic><topic>Switches</topic><topic>three-level T-type inverter (3LT<inline-formula xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> <tex-math notation="LaTeX"> ^2</tex-math> </inline-formula>I)</topic><topic>Topology</topic><topic>voltage boosting</topic><topic>Voltage reduction</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Qin, Changwei</creatorcontrib><creatorcontrib>Zhang, Chenghui</creatorcontrib><creatorcontrib>Chen, Alian</creatorcontrib><creatorcontrib>Xing, Xiangyang</creatorcontrib><creatorcontrib>Zhang, Guangxian</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on industrial electronics (1982)</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Qin, Changwei</au><au>Zhang, Chenghui</au><au>Chen, Alian</au><au>Xing, Xiangyang</au><au>Zhang, Guangxian</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A Space Vector Modulation Scheme of the Quasi-Z-Source Three-Level T-Type Inverter for Common-Mode Voltage Reduction</atitle><jtitle>IEEE transactions on industrial electronics (1982)</jtitle><stitle>TIE</stitle><date>2018-10-01</date><risdate>2018</risdate><volume>65</volume><issue>10</issue><spage>8340</spage><epage>8350</epage><pages>8340-8350</pages><issn>0278-0046</issn><eissn>1557-9948</eissn><coden>ITIED6</coden><abstract>The conventional three-level inverter suffers the limitation of voltage buck operation. In order to give both voltage buck and boost operation capability, the quasi-Z-source three-level T-type inverter (3LT 2 I) has been proposed. This paper further proposes a space vector modulation (SVM) scheme for the quasi-Z-source 3LT 2 I to reduce the magnitude and slew rate of common-mode voltage (CMV). By properly selecting the shoot-through phase, the shoot-through states are inserted within zero vector in order not to affect the active states and output voltage. Doing so, the CMV generated by the quasi-Z-source 3LT 2 I is restricted within one-sixth of dc-link voltage, and voltage boosting and CMV reduction can be simultaneously realized. In addition, high dc-link voltage utilization can be maintained. The proposed scheme has been verified in both simulations and experiments. Comparisons are conducted with the conventional SVM method and the phase-shifted sinusoidal PWM method.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TIE.2018.2798611</doi><tpages>11</tpages><orcidid>https://orcid.org/0000-0002-4467-0677</orcidid><orcidid>https://orcid.org/0000-0001-7078-7783</orcidid><orcidid>https://orcid.org/0000-0003-4919-4662</orcidid></addata></record> |
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| subjects | Boosting Common-mode voltage (CMV) reduction Electric potential Inverters Modulation Network topology quasi-Z-source Slew rate Space vector modulation Support vector machines Switches three-level T-type inverter (3LT<inline-formula xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> <tex-math notation="LaTeX"> ^2</tex-math> </inline-formula>I) Topology voltage boosting Voltage reduction |
| title | A Space Vector Modulation Scheme of the Quasi-Z-Source Three-Level T-Type Inverter for Common-Mode Voltage Reduction |
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