RS flip-flop implementation based on all spin logic devices
All spin logic (ASL) device is one of the promising post-CMOS candidates. Owing to unique features such as non-volatility, simple configuration, ultra-low-switching energy, and good scalability, ASL devices can be exploited in logic applications. Based on the characteristics of non-volatility and bi...
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| Veröffentlicht in: | Micro & nano letters 2017-06, Vol.12 (6), p.396-400 |
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| container_title | Micro & nano letters |
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| creator | Wang, Sen Cai, Li Feng, Chaowen Cui, Huanqing Yang, Xiaokuo Zhao, Hongyan |
| description | All spin logic (ASL) device is one of the promising post-CMOS candidates. Owing to unique features such as non-volatility, simple configuration, ultra-low-switching energy, and good scalability, ASL devices can be exploited in logic applications. Based on the characteristics of non-volatility and bistable states of ASL device, an RS flip-flop is proposed which is composed of seven ASL devices and employs a complementary clock signal scheme. Using the coupled spin-transport/magneto-dynamics model, validity of its logic operation is demonstrated. As a fundamental building block of sequential logic circuits, the proposed RS flip-flop will be an useful component for designing large-scale ASL sequential logic circuits. |
| doi_str_mv | 10.1049/mnl.2016.0589 |
| format | Article |
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Owing to unique features such as non-volatility, simple configuration, ultra-low-switching energy, and good scalability, ASL devices can be exploited in logic applications. Based on the characteristics of non-volatility and bistable states of ASL device, an RS flip-flop is proposed which is composed of seven ASL devices and employs a complementary clock signal scheme. Using the coupled spin-transport/magneto-dynamics model, validity of its logic operation is demonstrated. As a fundamental building block of sequential logic circuits, the proposed RS flip-flop will be an useful component for designing large-scale ASL sequential logic circuits.</description><identifier>ISSN: 1750-0443</identifier><identifier>EISSN: 1750-0443</identifier><identifier>DOI: 10.1049/mnl.2016.0589</identifier><language>eng</language><publisher>Stevenage: The Institution of Engineering and Technology</publisher><subject>all spin logic devices ; Circuit design ; clocks ; CMOS ; complementary clock signal scheme ; coupled spin‐transport ; flip‐flops ; Logic circuits ; logic design ; magneto‐dynamics model ; RS flip‐flop ; sequential logic circuits ; Spin dynamics ; Volatility</subject><ispartof>Micro & nano letters, 2017-06, Vol.12 (6), p.396-400</ispartof><rights>The Institution of Engineering and Technology</rights><rights>2017 The Institution of Engineering and Technology</rights><rights>Copyright The Institution of Engineering & Technology Jun 2017</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c3768-dffa2b229c2249d49a769675ca86a1e921969d7f4740d3dd80d3bdf5afeaf3e53</citedby><cites>FETCH-LOGICAL-c3768-dffa2b229c2249d49a769675ca86a1e921969d7f4740d3dd80d3bdf5afeaf3e53</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://onlinelibrary.wiley.com/doi/pdf/10.1049%2Fmnl.2016.0589$$EPDF$$P50$$Gwiley$$H</linktopdf><linktohtml>$$Uhttps://onlinelibrary.wiley.com/doi/full/10.1049%2Fmnl.2016.0589$$EHTML$$P50$$Gwiley$$H</linktohtml><link.rule.ids>314,780,784,1416,11561,27923,27924,45573,45574,46051,46475</link.rule.ids><linktorsrc>$$Uhttps://onlinelibrary.wiley.com/doi/abs/10.1049%2Fmnl.2016.0589$$EView_record_in_Wiley-Blackwell$$FView_record_in_$$GWiley-Blackwell</linktorsrc></links><search><creatorcontrib>Wang, Sen</creatorcontrib><creatorcontrib>Cai, Li</creatorcontrib><creatorcontrib>Feng, Chaowen</creatorcontrib><creatorcontrib>Cui, Huanqing</creatorcontrib><creatorcontrib>Yang, Xiaokuo</creatorcontrib><creatorcontrib>Zhao, Hongyan</creatorcontrib><title>RS flip-flop implementation based on all spin logic devices</title><title>Micro & nano letters</title><description>All spin logic (ASL) device is one of the promising post-CMOS candidates. Owing to unique features such as non-volatility, simple configuration, ultra-low-switching energy, and good scalability, ASL devices can be exploited in logic applications. Based on the characteristics of non-volatility and bistable states of ASL device, an RS flip-flop is proposed which is composed of seven ASL devices and employs a complementary clock signal scheme. Using the coupled spin-transport/magneto-dynamics model, validity of its logic operation is demonstrated. As a fundamental building block of sequential logic circuits, the proposed RS flip-flop will be an useful component for designing large-scale ASL sequential logic circuits.</description><subject>all spin logic devices</subject><subject>Circuit design</subject><subject>clocks</subject><subject>CMOS</subject><subject>complementary clock signal scheme</subject><subject>coupled spin‐transport</subject><subject>flip‐flops</subject><subject>Logic circuits</subject><subject>logic design</subject><subject>magneto‐dynamics model</subject><subject>RS flip‐flop</subject><subject>sequential logic circuits</subject><subject>Spin dynamics</subject><subject>Volatility</subject><issn>1750-0443</issn><issn>1750-0443</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2017</creationdate><recordtype>article</recordtype><recordid>eNp9kL1PwzAQxS0EEqUwsltCDAwptuPYsZhKRQGpLRIfs-XGNnLlfBCnoP73OApDh4rl7g2_u3f3ALjEaIIRFbdl5ScEYTZBWS6OwAjzDCWI0vR4T5-CsxA2CFFOuBiBu9c3aL1rEuvrBrqy8aY0Vac6V1dwrYLRMArlPQyNq6CvP10Btfl2hQnn4MQqH8zFXx-Dj_nD--wpWbw8Ps-mi6RIOcsTba0ia0JEQQgVmgrFmWA8K1TOFDaCYMGE5pZyinSqdR7rWttMWaNsarJ0DK6GvU1bf21N6OSm3rZVtJRYiPhU3JdHKhmooq1DaI2VTetK1e4kRrLPR8Z8ZJ-P7POJPBv4H-fN7n9YLldTcj9HGKW90fUw6MzeJcvVYo9vtI3czQHu8DG_HG-Bww</recordid><startdate>201706</startdate><enddate>201706</enddate><creator>Wang, Sen</creator><creator>Cai, Li</creator><creator>Feng, Chaowen</creator><creator>Cui, Huanqing</creator><creator>Yang, Xiaokuo</creator><creator>Zhao, Hongyan</creator><general>The Institution of Engineering and Technology</general><general>John Wiley & Sons, Inc</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7TB</scope><scope>7U5</scope><scope>8FD</scope><scope>F28</scope><scope>FR3</scope><scope>L7M</scope></search><sort><creationdate>201706</creationdate><title>RS flip-flop implementation based on all spin logic devices</title><author>Wang, Sen ; Cai, Li ; Feng, Chaowen ; Cui, Huanqing ; Yang, Xiaokuo ; Zhao, Hongyan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c3768-dffa2b229c2249d49a769675ca86a1e921969d7f4740d3dd80d3bdf5afeaf3e53</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2017</creationdate><topic>all spin logic devices</topic><topic>Circuit design</topic><topic>clocks</topic><topic>CMOS</topic><topic>complementary clock signal scheme</topic><topic>coupled spin‐transport</topic><topic>flip‐flops</topic><topic>Logic circuits</topic><topic>logic design</topic><topic>magneto‐dynamics model</topic><topic>RS flip‐flop</topic><topic>sequential logic circuits</topic><topic>Spin dynamics</topic><topic>Volatility</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Wang, Sen</creatorcontrib><creatorcontrib>Cai, Li</creatorcontrib><creatorcontrib>Feng, Chaowen</creatorcontrib><creatorcontrib>Cui, Huanqing</creatorcontrib><creatorcontrib>Yang, Xiaokuo</creatorcontrib><creatorcontrib>Zhao, Hongyan</creatorcontrib><collection>CrossRef</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Micro & nano letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Wang, Sen</au><au>Cai, Li</au><au>Feng, Chaowen</au><au>Cui, Huanqing</au><au>Yang, Xiaokuo</au><au>Zhao, Hongyan</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>RS flip-flop implementation based on all spin logic devices</atitle><jtitle>Micro & nano letters</jtitle><date>2017-06</date><risdate>2017</risdate><volume>12</volume><issue>6</issue><spage>396</spage><epage>400</epage><pages>396-400</pages><issn>1750-0443</issn><eissn>1750-0443</eissn><abstract>All spin logic (ASL) device is one of the promising post-CMOS candidates. Owing to unique features such as non-volatility, simple configuration, ultra-low-switching energy, and good scalability, ASL devices can be exploited in logic applications. Based on the characteristics of non-volatility and bistable states of ASL device, an RS flip-flop is proposed which is composed of seven ASL devices and employs a complementary clock signal scheme. Using the coupled spin-transport/magneto-dynamics model, validity of its logic operation is demonstrated. As a fundamental building block of sequential logic circuits, the proposed RS flip-flop will be an useful component for designing large-scale ASL sequential logic circuits.</abstract><cop>Stevenage</cop><pub>The Institution of Engineering and Technology</pub><doi>10.1049/mnl.2016.0589</doi><tpages>5</tpages></addata></record> |
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| source | Wiley Online Library Open Access |
| subjects | all spin logic devices Circuit design clocks CMOS complementary clock signal scheme coupled spin‐transport flip‐flops Logic circuits logic design magneto‐dynamics model RS flip‐flop sequential logic circuits Spin dynamics Volatility |
| title | RS flip-flop implementation based on all spin logic devices |
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