Region-based dual bank register allocation for reduced instruction encoding Architectures

In embedded systems, small code size is important due to memory constraints. One technique to achieve a small code size is reducing the instruction encoding from 32-bit to 16-bit, such as the ARM THUMB or MIPS-16 architectures. This half-size encoding leads to shorter register operands, making fewer...

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Veröffentlicht in:	Microprocessors and microsystems 2017-11, Vol.55, p.26-43
Hauptverfasser:	Lee, Je-Hyung, Moon, Soo-Mook, Park, Jinpyo
Format:	Artikel
Sprache:	eng
Schlagworte:	Architecture Banked registers Banks Central processing units Coding CPUs Embedded systems Reduced encoding architectures Register allocation Registers Spills
Online-Zugang:	Volltext
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