Study on Low Warpage and High Reliability for Large Package Using TSV-Free Interposer Technology Through SMART Codesign Modeling
Through-silicon via (TSV)-free interposer (TFI) technology eliminates TSV fabrication and reduces manufacturing and material cost. In this paper, structure-material-assembly-reliability-thermal (SMART) codesign modeling methodology is established for a package using TFI technology by considering waf...
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| Veröffentlicht in: | IEEE transactions on components, packaging, and manufacturing technology (2011) packaging, and manufacturing technology (2011), 2017-11, Vol.7 (11), p.1774-1785 |
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| container_title | IEEE transactions on components, packaging, and manufacturing technology (2011) |
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| creator | Fa Xing Che Kawano, Masaya Mian Zhi Ding Yong Han Bhattacharya, Surya |
| description | Through-silicon via (TSV)-free interposer (TFI) technology eliminates TSV fabrication and reduces manufacturing and material cost. In this paper, structure-material-assembly-reliability-thermal (SMART) codesign modeling methodology is established for a package using TFI technology by considering wafer process, package assembly and package/board-level temperature cycling reliability, and thermal performance to optimize structure design, assembly process, and material selection. Experimental results are used to validate wafer warpage modeling results first. Through wafer-level modeling, suitable carrier and molding compound materials are recommended to control wafer warpage less than 2 mm for 12-in molded wafer. Effects of coefficient of thermal expansion of package substrate and stiffener on package warpage induced by assembly reflow process are simulated and analyzed. The recommended materials and geometry design based on thermal cycling reliability simulation are aligned with that from wafer and package warpage simulation results. The final test vehicle design and material selection are determined based on SMART codesign modeling results for achieving successful TFI wafer process and package assembly and long-term board-level reliability. |
| doi_str_mv | 10.1109/TCPMT.2017.2707567 |
| format | Article |
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In this paper, structure-material-assembly-reliability-thermal (SMART) codesign modeling methodology is established for a package using TFI technology by considering wafer process, package assembly and package/board-level temperature cycling reliability, and thermal performance to optimize structure design, assembly process, and material selection. Experimental results are used to validate wafer warpage modeling results first. Through wafer-level modeling, suitable carrier and molding compound materials are recommended to control wafer warpage less than 2 mm for 12-in molded wafer. Effects of coefficient of thermal expansion of package substrate and stiffener on package warpage induced by assembly reflow process are simulated and analyzed. The recommended materials and geometry design based on thermal cycling reliability simulation are aligned with that from wafer and package warpage simulation results. The final test vehicle design and material selection are determined based on SMART codesign modeling results for achieving successful TFI wafer process and package assembly and long-term board-level reliability.</description><identifier>ISSN: 2156-3950</identifier><identifier>EISSN: 2156-3985</identifier><identifier>DOI: 10.1109/TCPMT.2017.2707567</identifier><identifier>CODEN: ITCPC8</identifier><language>eng</language><publisher>Piscataway: IEEE</publisher><subject>Assembly ; Co-design ; Computer simulation ; Design optimization ; Electromagnetic compatibility ; Finite-element analysis (FEA) ; Materials selection ; Modelling ; Molding (process) ; Reliability engineering ; Semiconductor device modeling ; Semiconductor device reliability ; Silicon ; solder joint reliability ; Soldering ; Solid modeling ; Structural reliability ; structure–material–assembly–reliability–thermal (SMART) codesign modeling ; Technology utilization ; Test vehicles ; Thermal cycling ; Thermal expansion ; through-silicon via (TSV)-free interposer technology ; Warpage</subject><ispartof>IEEE transactions on components, packaging, and manufacturing technology (2011), 2017-11, Vol.7 (11), p.1774-1785</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2017</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c295t-2054b79da25b00c0b9450ddb56ce21eebf6c4bca963f5903ce218945f68773e33</citedby><cites>FETCH-LOGICAL-c295t-2054b79da25b00c0b9450ddb56ce21eebf6c4bca963f5903ce218945f68773e33</cites><orcidid>0000-0002-1564-1340 ; 0000-0003-2326-6568</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/7948771$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27923,27924,54757</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/7948771$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Fa Xing Che</creatorcontrib><creatorcontrib>Kawano, Masaya</creatorcontrib><creatorcontrib>Mian Zhi Ding</creatorcontrib><creatorcontrib>Yong Han</creatorcontrib><creatorcontrib>Bhattacharya, Surya</creatorcontrib><title>Study on Low Warpage and High Reliability for Large Package Using TSV-Free Interposer Technology Through SMART Codesign Modeling</title><title>IEEE transactions on components, packaging, and manufacturing technology (2011)</title><addtitle>TCPMT</addtitle><description>Through-silicon via (TSV)-free interposer (TFI) technology eliminates TSV fabrication and reduces manufacturing and material cost. In this paper, structure-material-assembly-reliability-thermal (SMART) codesign modeling methodology is established for a package using TFI technology by considering wafer process, package assembly and package/board-level temperature cycling reliability, and thermal performance to optimize structure design, assembly process, and material selection. Experimental results are used to validate wafer warpage modeling results first. Through wafer-level modeling, suitable carrier and molding compound materials are recommended to control wafer warpage less than 2 mm for 12-in molded wafer. Effects of coefficient of thermal expansion of package substrate and stiffener on package warpage induced by assembly reflow process are simulated and analyzed. The recommended materials and geometry design based on thermal cycling reliability simulation are aligned with that from wafer and package warpage simulation results. The final test vehicle design and material selection are determined based on SMART codesign modeling results for achieving successful TFI wafer process and package assembly and long-term board-level reliability.</description><subject>Assembly</subject><subject>Co-design</subject><subject>Computer simulation</subject><subject>Design optimization</subject><subject>Electromagnetic compatibility</subject><subject>Finite-element analysis (FEA)</subject><subject>Materials selection</subject><subject>Modelling</subject><subject>Molding (process)</subject><subject>Reliability engineering</subject><subject>Semiconductor device modeling</subject><subject>Semiconductor device reliability</subject><subject>Silicon</subject><subject>solder joint reliability</subject><subject>Soldering</subject><subject>Solid modeling</subject><subject>Structural reliability</subject><subject>structure–material–assembly–reliability–thermal (SMART) codesign modeling</subject><subject>Technology utilization</subject><subject>Test vehicles</subject><subject>Thermal cycling</subject><subject>Thermal expansion</subject><subject>through-silicon via (TSV)-free interposer technology</subject><subject>Warpage</subject><issn>2156-3950</issn><issn>2156-3985</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2017</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9UF1PwjAUXYwmEuQP6EsTn4dtt7b0kSwiJBAJDH1cuu1uDOc62y2GN3-6RQz35Z7cez6S43n3BI8JwfIpjtareEwxEWMqsGBcXHkDShj3Azlh1xfM8K03svaA3bAJFjgYeD_brs-PSDdoqb_RuzKtKgGpJkfzqtyjDdSVSqu66o6o0AYtlXHvtco-TrSdrZoSxds3f2YA0KLpwLTagkExZPtG17o8onhvdO-stqvpJkaRzsFWZYNWDtROfufdFKq2MPrfQ283e46jub98fVlE06WfUck6n2IWpkLmirIU4wynMmQ4z1PGM6AEIC14FqaZkjwomMTB6TpxnIJPhAggCIbe49m3NfqrB9slB92bxkUmRDIeUo5D4Vj0zMqMttZAkbSm-lTmmBCcnMpO_spOTmUn_2U70cNZVAHARSBk6KJJ8AuK-3r8</recordid><startdate>20171101</startdate><enddate>20171101</enddate><creator>Fa Xing Che</creator><creator>Kawano, Masaya</creator><creator>Mian Zhi Ding</creator><creator>Yong Han</creator><creator>Bhattacharya, Surya</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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In this paper, structure-material-assembly-reliability-thermal (SMART) codesign modeling methodology is established for a package using TFI technology by considering wafer process, package assembly and package/board-level temperature cycling reliability, and thermal performance to optimize structure design, assembly process, and material selection. Experimental results are used to validate wafer warpage modeling results first. Through wafer-level modeling, suitable carrier and molding compound materials are recommended to control wafer warpage less than 2 mm for 12-in molded wafer. Effects of coefficient of thermal expansion of package substrate and stiffener on package warpage induced by assembly reflow process are simulated and analyzed. The recommended materials and geometry design based on thermal cycling reliability simulation are aligned with that from wafer and package warpage simulation results. The final test vehicle design and material selection are determined based on SMART codesign modeling results for achieving successful TFI wafer process and package assembly and long-term board-level reliability.</abstract><cop>Piscataway</cop><pub>IEEE</pub><doi>10.1109/TCPMT.2017.2707567</doi><tpages>12</tpages><orcidid>https://orcid.org/0000-0002-1564-1340</orcidid><orcidid>https://orcid.org/0000-0003-2326-6568</orcidid></addata></record> |
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| subjects | Assembly Co-design Computer simulation Design optimization Electromagnetic compatibility Finite-element analysis (FEA) Materials selection Modelling Molding (process) Reliability engineering Semiconductor device modeling Semiconductor device reliability Silicon solder joint reliability Soldering Solid modeling Structural reliability structure–material–assembly–reliability–thermal (SMART) codesign modeling Technology utilization Test vehicles Thermal cycling Thermal expansion through-silicon via (TSV)-free interposer technology Warpage |
| title | Study on Low Warpage and High Reliability for Large Package Using TSV-Free Interposer Technology Through SMART Codesign Modeling |
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