Design of Low Power Phase Detector in 0.13 urn CMOS

This paper presents a designed of Phase Detector (PD) which applied into the Phase Locked Loop (PLL) circuits which commonly used in the system of communication. Currently, the design and development of low power PD are always crucial concerned by circuits designer to minimize the power consuming. The primary goal of this work is to design a low power PD. The architectures of PD also reduce the complexity structure of the circuit. To varying the low power, the resistor in the circuits was replaced and utilized with PMOS and current bias with NMOS transistor. Providing power supply 1.8 V, the PD dissipated to 20.9 mW of its power. This proposed PD was designed in Mentor Graphics environment by using 0.13-pm CMOS process technology, TSMC.