Low power PLL with reduced reference spur realized with glitch-free linear PFD and current splitting CP
This work has been focused on designing a phase locked loop (PLL) operating in the GHz range with reduced reference spur and power requirement suitable for wireless communication applications such as wireless receivers, serial link trans-receivers and military communication. A novel PLL is designed...
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Veröffentlicht in: | Analog integrated circuits and signal processing 2017-10, Vol.93 (1), p.29-39 |
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creator | Abdul Majeed, K. K. Kailath, Binsu J. |
description | This work has been focused on designing a phase locked loop (PLL) operating in the GHz range with reduced reference spur and power requirement suitable for wireless communication applications such as wireless receivers, serial link trans-receivers and military communication. A novel PLL is designed using a linear PFD which is free of glitches, dead zone and blind zone, a charge pump based on current splitting technique and a modified current starved differential delay cell (MCSDD) VCO. Performance characteristics of proposed PLL obtained from circuit simulation in Cadence have been compared with simulation results from MATLAB. φ–V characteristics of linear PFD has been found to offer better linearity from −π to π as blind zone and dead zone are eliminated. Glitches at output of PFD have also been eliminated. Charge pump based on current splitting technique in combination with proposed PFD has been found to be effective in reducing leakage current to 3 nA. Tuning range of 98.12% with maximum operating frequency of 4.27 GHz has been obtained for the MCSDD VCO. PLL built with above circuits has been found to offer reference spur of −75.92 dBc@20 MHz offset, phase noise of −113.5 dBc/Hz@100 kHz and lock time of 2.95 μs. It is believed to be the first report of linear PFD in which glitches are completely eliminated. The PLL would be suitable for low power, low noise and high frequency applications as required in mobile communications operating around 20 MHz, to be derived from the VCO when set to generate a frequency of 2.56 GHz. |
doi_str_mv | 10.1007/s10470-017-1013-4 |
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K. ; Kailath, Binsu J.</creator><creatorcontrib>Abdul Majeed, K. K. ; Kailath, Binsu J.</creatorcontrib><description>This work has been focused on designing a phase locked loop (PLL) operating in the GHz range with reduced reference spur and power requirement suitable for wireless communication applications such as wireless receivers, serial link trans-receivers and military communication. A novel PLL is designed using a linear PFD which is free of glitches, dead zone and blind zone, a charge pump based on current splitting technique and a modified current starved differential delay cell (MCSDD) VCO. Performance characteristics of proposed PLL obtained from circuit simulation in Cadence have been compared with simulation results from MATLAB. φ–V characteristics of linear PFD has been found to offer better linearity from −π to π as blind zone and dead zone are eliminated. Glitches at output of PFD have also been eliminated. Charge pump based on current splitting technique in combination with proposed PFD has been found to be effective in reducing leakage current to 3 nA. Tuning range of 98.12% with maximum operating frequency of 4.27 GHz has been obtained for the MCSDD VCO. PLL built with above circuits has been found to offer reference spur of −75.92 dBc@20 MHz offset, phase noise of −113.5 dBc/Hz@100 kHz and lock time of 2.95 μs. It is believed to be the first report of linear PFD in which glitches are completely eliminated. The PLL would be suitable for low power, low noise and high frequency applications as required in mobile communications operating around 20 MHz, to be derived from the VCO when set to generate a frequency of 2.56 GHz.</description><identifier>ISSN: 0925-1030</identifier><identifier>EISSN: 1573-1979</identifier><identifier>DOI: 10.1007/s10470-017-1013-4</identifier><language>eng</language><publisher>New York: Springer US</publisher><subject>Charge pumps ; Circuits and Systems ; Electrical Engineering ; Engineering ; Leakage current ; Linearity ; Low noise ; Military communications ; Mobile communication systems ; Noise reduction ; Receivers ; Signal,Image and Speech Processing ; Splitting ; Wireless communications</subject><ispartof>Analog integrated circuits and signal processing, 2017-10, Vol.93 (1), p.29-39</ispartof><rights>Springer Science+Business Media, LLC 2017</rights><rights>Copyright Springer Science & Business Media 2017</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c316t-98cd037403df4f2bee544528ec795fbdcd08f6363ac786235684c3843affc6ad3</citedby><cites>FETCH-LOGICAL-c316t-98cd037403df4f2bee544528ec795fbdcd08f6363ac786235684c3843affc6ad3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://link.springer.com/content/pdf/10.1007/s10470-017-1013-4$$EPDF$$P50$$Gspringer$$H</linktopdf><linktohtml>$$Uhttps://link.springer.com/10.1007/s10470-017-1013-4$$EHTML$$P50$$Gspringer$$H</linktohtml><link.rule.ids>314,780,784,27924,27925,41488,42557,51319</link.rule.ids></links><search><creatorcontrib>Abdul Majeed, K. K.</creatorcontrib><creatorcontrib>Kailath, Binsu J.</creatorcontrib><title>Low power PLL with reduced reference spur realized with glitch-free linear PFD and current splitting CP</title><title>Analog integrated circuits and signal processing</title><addtitle>Analog Integr Circ Sig Process</addtitle><description>This work has been focused on designing a phase locked loop (PLL) operating in the GHz range with reduced reference spur and power requirement suitable for wireless communication applications such as wireless receivers, serial link trans-receivers and military communication. A novel PLL is designed using a linear PFD which is free of glitches, dead zone and blind zone, a charge pump based on current splitting technique and a modified current starved differential delay cell (MCSDD) VCO. Performance characteristics of proposed PLL obtained from circuit simulation in Cadence have been compared with simulation results from MATLAB. φ–V characteristics of linear PFD has been found to offer better linearity from −π to π as blind zone and dead zone are eliminated. Glitches at output of PFD have also been eliminated. Charge pump based on current splitting technique in combination with proposed PFD has been found to be effective in reducing leakage current to 3 nA. Tuning range of 98.12% with maximum operating frequency of 4.27 GHz has been obtained for the MCSDD VCO. PLL built with above circuits has been found to offer reference spur of −75.92 dBc@20 MHz offset, phase noise of −113.5 dBc/Hz@100 kHz and lock time of 2.95 μs. It is believed to be the first report of linear PFD in which glitches are completely eliminated. The PLL would be suitable for low power, low noise and high frequency applications as required in mobile communications operating around 20 MHz, to be derived from the VCO when set to generate a frequency of 2.56 GHz.</description><subject>Charge pumps</subject><subject>Circuits and Systems</subject><subject>Electrical Engineering</subject><subject>Engineering</subject><subject>Leakage current</subject><subject>Linearity</subject><subject>Low noise</subject><subject>Military communications</subject><subject>Mobile communication systems</subject><subject>Noise reduction</subject><subject>Receivers</subject><subject>Signal,Image and Speech Processing</subject><subject>Splitting</subject><subject>Wireless communications</subject><issn>0925-1030</issn><issn>1573-1979</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2017</creationdate><recordtype>article</recordtype><recordid>eNp1kD9PwzAQxS0EEqXwAdgsMRvOsRM7Iyp_pUh0gNlKHTtNFZJgJ6rg03MlDCxMp7t7v3f2I-SSwzUHUDeRg1TAgCvGgQsmj8iCp0ownqv8mCwgT1LcCDglZzHuACBREhakLvo9Hfq9C3RdFHTfjFsaXDVZV2H1LrjOOhqHKWBbts0Xzn9EdduMdst8cI62TedKNHi4o2VXUTsFxEakUDM2XU1X63Ny4ss2uovfuiRvD_evqydWvDw-r24LZgXPRpZrW4HAl4nKS59snEulTBPtrMpTv6lwq30mMlFapbNEpJmWVmgpSu9tVlZiSa5m3yH0H5OLo9n1U-jwpOG5UBpSrjWq-KyyoY8R_2mG0LyX4dNwMIc8zZynwTzNIU8jkUlmJqK2q1344_wv9A1Q1XgS</recordid><startdate>20171001</startdate><enddate>20171001</enddate><creator>Abdul Majeed, K. K.</creator><creator>Kailath, Binsu J.</creator><general>Springer US</general><general>Springer Nature B.V</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>7TG</scope><scope>8FD</scope><scope>KL.</scope><scope>L7M</scope></search><sort><creationdate>20171001</creationdate><title>Low power PLL with reduced reference spur realized with glitch-free linear PFD and current splitting CP</title><author>Abdul Majeed, K. K. ; Kailath, Binsu J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c316t-98cd037403df4f2bee544528ec795fbdcd08f6363ac786235684c3843affc6ad3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2017</creationdate><topic>Charge pumps</topic><topic>Circuits and Systems</topic><topic>Electrical Engineering</topic><topic>Engineering</topic><topic>Leakage current</topic><topic>Linearity</topic><topic>Low noise</topic><topic>Military communications</topic><topic>Mobile communication systems</topic><topic>Noise reduction</topic><topic>Receivers</topic><topic>Signal,Image and Speech Processing</topic><topic>Splitting</topic><topic>Wireless communications</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Abdul Majeed, K. K.</creatorcontrib><creatorcontrib>Kailath, Binsu J.</creatorcontrib><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Meteorological & Geoastrophysical Abstracts</collection><collection>Technology Research Database</collection><collection>Meteorological & Geoastrophysical Abstracts - Academic</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Analog integrated circuits and signal processing</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Abdul Majeed, K. K.</au><au>Kailath, Binsu J.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Low power PLL with reduced reference spur realized with glitch-free linear PFD and current splitting CP</atitle><jtitle>Analog integrated circuits and signal processing</jtitle><stitle>Analog Integr Circ Sig Process</stitle><date>2017-10-01</date><risdate>2017</risdate><volume>93</volume><issue>1</issue><spage>29</spage><epage>39</epage><pages>29-39</pages><issn>0925-1030</issn><eissn>1573-1979</eissn><abstract>This work has been focused on designing a phase locked loop (PLL) operating in the GHz range with reduced reference spur and power requirement suitable for wireless communication applications such as wireless receivers, serial link trans-receivers and military communication. A novel PLL is designed using a linear PFD which is free of glitches, dead zone and blind zone, a charge pump based on current splitting technique and a modified current starved differential delay cell (MCSDD) VCO. Performance characteristics of proposed PLL obtained from circuit simulation in Cadence have been compared with simulation results from MATLAB. φ–V characteristics of linear PFD has been found to offer better linearity from −π to π as blind zone and dead zone are eliminated. Glitches at output of PFD have also been eliminated. Charge pump based on current splitting technique in combination with proposed PFD has been found to be effective in reducing leakage current to 3 nA. Tuning range of 98.12% with maximum operating frequency of 4.27 GHz has been obtained for the MCSDD VCO. PLL built with above circuits has been found to offer reference spur of −75.92 dBc@20 MHz offset, phase noise of −113.5 dBc/Hz@100 kHz and lock time of 2.95 μs. It is believed to be the first report of linear PFD in which glitches are completely eliminated. The PLL would be suitable for low power, low noise and high frequency applications as required in mobile communications operating around 20 MHz, to be derived from the VCO when set to generate a frequency of 2.56 GHz.</abstract><cop>New York</cop><pub>Springer US</pub><doi>10.1007/s10470-017-1013-4</doi><tpages>11</tpages></addata></record> |
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subjects | Charge pumps Circuits and Systems Electrical Engineering Engineering Leakage current Linearity Low noise Military communications Mobile communication systems Noise reduction Receivers Signal,Image and Speech Processing Splitting Wireless communications |
title | Low power PLL with reduced reference spur realized with glitch-free linear PFD and current splitting CP |
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