The design and realization of a new high speed FPGA-based chaotic true random number generator

•Sundarapandian–Pehlivan chaotic system (SPCS) has been modeled and simulated in three distinct platforms (Numerical, Pspice and FPGA-based).•SPCS has been modeled in VHDL language by using RK4 algorithm and has been synthesized for Xilinx Virtex-6 FPGA chip in development environment.•The maximum o...

Ausführliche Beschreibung